Semiconductor Memory Cell Structure with Shared Selector
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Solution Overview
Problem
Current semiconductor memory devices face challenges in miniaturization, low power consumption, and cost-effective fabrication processes, particularly in integrating memory cells with reduced complexity and fabrication costs while maintaining performance.
Innovation Solution
The implementation of a semiconductor memory unit with a cell structure featuring two memory cells sharing a selector, symmetrically disposed electrodes, and a variable resistance pattern, along with a multi-stack structure that simplifies the fabrication process by using line-type and pillar-type electrodes, and interlayer insulation layers to reduce the number and complexity of fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional memory cell structures are used, then device functionality is maintained, but integration density is limited and fabrication complexity increases
Solution Approach 1:
The patent merges two memory cells into a single cell structure that shares one selector, reducing the number of discrete components. This consolidation increases integration density while simplifying the overall device architecture and fabrication process by eliminating redundant selector structures.
Solution Approach 2:
The patent transitions from planar memory cell arrangements to a vertical multi-stack structure, stacking multiple cell layers in the vertical dimension. This dimensional change dramatically increases integration density without proportionally increasing fabrication complexity, as the stacking approach can be implemented through sequential deposition processes.
2Quantity of substance
If more memory cells are integrated, then storage capacity increases, but fabrication process complexity and costs increase
Solution Approach 1:
The patent segments the memory device into standardized cell structures that can be repeatedly stacked vertically. Each cell structure contains two memory cells with shared components, creating a modular design that increases the number of memory cells through simple repetition rather than complex individual fabrication for each cell.
Solution Approach 2:
The shared selector structure serves multiple memory cells simultaneously, making it a universal component that performs the same selection function for both cells. This multi-functionality reduces the total number of selectors needed, simplifying fabrication while increasing the number of functional memory cells.
3Reliability
If complex electrode structures are used, then device performance is maintained, but fabrication steps and costs increase
Solution Approach 1:
The patent employs asymmetric electrode configurations where the first electrode and second electrode have different structural arrangements optimized for their specific functions. The first electrode is positioned to contact the variable resistance pattern, while the second electrode contacts the selector, creating an asymmetric but functionally optimized structure that maintains performance with simplified fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances integration, reduces fabrication complexity and costs, and improves processing margins by using line-type structures for memory cells, leading to more efficient and compact semiconductor devices.
Implementation Method 1
a variable resistance pattern and a second electrode, which are symmetrically disposed on both sides of the selector
Data Source
AI summary
An electronic device including a semiconductor memory unit that includes a cell structure having two memory cells, which share one selector, wherein the cell structure includes first electrodes, variable resistance patterns and second electrodes which are symmetrically disposed on both sides of the selector.