Semiconductor Memory Cell Layout With Shared Word Lines
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Solution Overview
Problem
The integration density of switch transistors in semiconductor structures is relatively low, limiting the number of memory cells that can be integrated in a given unit size, which affects the memory capacity.
Innovation Solution
A semiconductor structure design where only one word line is arranged between two adjacent active bodies, allowing simultaneous turn-on signals to be input to adjacent word lines to form a conductive channel, thereby reducing the space between active bodies and improving integration density, along with a manufacturing method that includes forming bit lines, active bodies, and word lines within an insulator, and doping semiconductor material to form source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple word lines are arranged between adjacent active bodies, then each word line can independently control memory cells, but the space between active bodies increases, reducing integration density
Solution Approach 1:
The patent merges the control function of multiple word lines into a single shared word line. Adjacent active bodies share the same word line, and simultaneous turn-on signals are applied to adjacent word lines to form conductive channels between bit lines and capacitors. This combining approach reduces the number of word lines needed while maintaining independent control capability through signal timing.
Solution Approach 2:
Each word line serves multiple functions: it acts as a control line for selecting memory cells and simultaneously forms part of the conductive channel when turned on. The word line structure is designed to be shared by adjacent active bodies, making it a universal element that performs both selection and conduction functions.
2Quantity of substance
If more memory cells are integrated in unit size, then memory capacity increases, but the space available for each memory cell decreases, making fabrication more difficult
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional structure by forming active bodies that extend vertically from the substrate. The bit lines are positioned at different heights (some on substrate, some in insulator), and word lines are formed in trenches within the insulator. This vertical stacking and multi-level arrangement increases integration density without proportionally reducing the fabrication area, thereby maintaining manufacturing precision while increasing memory cell count.
Solution Approach 2:
The patent implements a nested structure where active bodies are formed within the insulator material, word lines are embedded in trenches within the insulator, and bit lines are positioned both on the substrate and within the insulator. This nesting approach allows multiple components to occupy overlapping or adjacent spatial regions, effectively increasing the number of memory cells that can be packed into a given area while maintaining manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the integration density of memory cells on the semiconductor structure, allowing for a higher number of memory cells to be packed in a smaller area, thereby improving memory capacity.
Implementation Method 1
doping semiconductor material to form source and drain regions
Data Source
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AI summary
The present application relates to the technical field of storage and provides a semiconductor structure, and a manufacturing method and control method thereof. The semiconductor structure includes a base substrate, multiple bit lines, multiple active bodies, an insulator, and multiple word lines. The insulator is located on one side of the base substrate; the multiple bit lines are arranged in the insulator, and the multiple bit lines are distributed at intervals along a first direction and extend along a second direction; the multiple active bodies are located on sides of respective bit lines facing away from the base substrate, orthographic projection of each active body on the base substrate at least partially coincides with the orthographic projection of a respective bit line on the base substrate, and the active bodies are distributed at intervals along the second direction; the multiple word lines are located in the insulator and located on sides of respective bit lines facing away from the base substrate, the word lines are distributed at intervals along the second direction and extend along the first direction, and only one word line is arranged between two adjacent active bodies in the second direction. According to the semiconductor structure, more memory cells may be integrated in a limited space.