Semiconductor Memory Cell Source Impurity Segmentation
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Solution Overview
Problem
Existing semiconductor devices face issues with erroneous writing of information due to high voltage being applied to non-selected memory cell transistors, leading to random and unintended data corruption.
Innovation Solution
The semiconductor device incorporates a memory cell transistor with a floating gate and a selecting transistor, where the source of the selecting transistor is connected to the drain of the memory cell transistor, and the source of the memory cell transistor has a specific impurity diffusion layer structure to reduce erroneous writing by alleviating the electric field and suppressing carrier generation in non-selected memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high voltage is applied to a source line connected to sources of a plurality of memory cell transistors to write information, then writing speed is improved, but erroneous writing into non-selected memory cell transistors occurs
Solution Approach 1:
The source region is segmented into multiple impurity diffusion layers (first, second, and third N-type layers) with different impurity densities and depths. This segmentation allows different portions of the source to have different electrical characteristics, enabling high voltage to be applied for fast writing while the lower-impurity-density regions suppress carrier generation in non-selected cells, preventing erroneous writing.
Solution Approach 2:
Different regions of the source have different impurity densities tailored to their specific functions. The third impurity diffusion layer (shallower, higher density) provides strong carrier suppression for non-selected cells, while the first and second layers (deeper, lower density) allow sufficient current flow for selected cell writing. This local quality differentiation resolves the contradiction between fast writing and preventing erroneous writing.
2Device complexity
If a simple single-layer source structure is used, then device complexity is reduced, but carrier generation in non-selected memory cells cannot be sufficiently suppressed
Solution Approach 1:
The source is divided into three distinct impurity diffusion layers with progressively different characteristics. The third layer (highest impurity density, shallowest depth) specifically targets carrier suppression in non-selected cells, while the first and second layers maintain electrical connectivity. This segmented structure achieves reliable erroneous writing suppression without requiring overly complex multi-component designs.
Solution Approach 2:
The source structure utilizes parameter changes in impurity density and depth across three layers. By varying these parameters systematically (higher density and shallower depth for the third layer), the structure achieves effective carrier suppression in non-selected cells while maintaining simplicity through a regular, scalable design pattern that can be manufactured with standard semiconductor processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces erroneous writing into non-selected memory cells while maintaining high writing speed and accuracy for the selected memory cell, improving overall data integrity and storage efficiency.
Implementation Method 1
the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is formed in the second impurity diffusion layer
Implementation Method 2
an impurity density of the second impurity diffusion layer is lower than the impurity density of the third impurity diffusion layer
Implementation Method 3
when information is written into a memory cell, a high voltage is applied to a source line connected to a source of a memory cell transistor and a control gate of the memory cell transistor. As a result, hot electrons are generated and some of them are implanted into a floating gate of the memory cell transistor
Implementation Method 4
hot electrons are generated and some of them are implanted into a floating gate of the memory cell transistor
Data Source
AI summary
A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.