Memory Cell Stability Testing via Dummy Read Operations
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Solution Overview
Problem
Existing methods for testing the stability of memory cells in memory devices, particularly those using transistors with a body region insulated from the substrate, fail to reliably identify unstable cells due to the 'history effect,' which can lead to data corruption and cell failure, and often require additional dedicated test patterns or lengthy test procedures.
Innovation Solution
A data processing apparatus and method that employs dummy read control circuitry to generate an internal clock signal with increased frequency, performing a dummy read operation immediately after each write operation to stress memory cells and detect instability, allowing for the use of existing test patterns to identify defective cells without the need for dedicated stability testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistors with body region insulated from substrate are used to form memory cells, then switching speed increases and power dissipation decreases, but cell stability deteriorates due to body region voltage variation from history effect
Solution Approach 1:
The patent applies preliminary action by performing a dummy read operation immediately after a write operation to a memory cell. This dummy read is executed before any actual read operation to prevent data corruption caused by the history effect. The dummy read clears the unstable body region voltage state created by the write operation, ensuring subsequent reads occur when the cell is stable.
Solution Approach 2:
The patent applies preliminary anti-action by using the dummy read operation to counteract the harmful history effect before it can cause data corruption. The dummy read prevents the instability caused by body region voltage variation from affecting actual read operations, thereby protecting against the adverse effects of using insulated body region transistors.
2Measurement precision
If dedicated test patterns are developed to test for history effect-induced instability, then detection accuracy improves, but device complexity and test time increase
Solution Approach 1:
The patent applies universality by making the dummy read operation part of the standard memory access protocol that can be integrated into existing test patterns. Rather than requiring separate dedicated test patterns, the dummy read mechanism works with any existing test pattern that includes write operations, making the solution universally applicable to all memory cell testing scenarios.
Solution Approach 2:
The patent applies self-service by using the memory device's own read circuitry to perform the dummy read operation. The existing read mechanism is utilized to clear the unstable state, eliminating the need for additional specialized testing circuitry or complex external test equipment.
Data Source
AI summary
A data processor includes a memory device having an array of memory cells for storing data values. Test circuitry executes one or more test patterns to detect any memory cells which may malfunction. Each test pattern causes a sequence of access requests to be issued to the memory device where the timing of the sequence is controlled by a test mode clock signal. Dummy read control circuitry is responsive at least to each write access request to generate an internal clock signal which has an increased frequency with respect to the test mode clock signal. The dummy read control circuitry performs, using the internal clock signal, a write operation to at least one memory cell based on a memory address specified by the write access request, followed by a dummy read operation to the same memory cell, serving to stress the memory cell with respect to cell stability.