Memory Cell State Division for Low Latency Flash Read Operations
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Solution Overview
Problem
Multi-level cell (MLC) flash memory devices require multiple sensing operations to determine the state of each cell, leading to increased read latency, while single-level cell (SLC) flash memories have lower storage density and higher latency.
Innovation Solution
The implementation of a coding scheme that divides memory cell states into two sets, allowing data to be read using a single sensing operation by determining whether each cell is in a first or second set of states, thereby reducing the number of sense operations needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple sensing operations are performed to determine the state of each MLC cell, then storage density is improved, but read latency increases
Solution Approach 1:
The patent segments the 3-bit data stored in each MLC cell into multiple groups, where each group can be read using a single sensing operation. By dividing the data bits into separate groups and storing them in different cell states, the system enables selective reading of individual groups without requiring multiple sensing operations, thus reducing read latency while maintaining high storage density
Solution Approach 2:
The patent implements dynamic read operations where the sensing operation adapts based on which group of data bits needs to be read. By dynamically selecting the appropriate sensing threshold and operation based on the requested data group, the system achieves fast random read performance comparable to SLC memory while maintaining MLC storage density
2Loss of time
If SLC flash memory is used instead of MLC, then read latency is reduced, but storage density decreases
Solution Approach 1:
The patent applies segmentation by dividing the 3-bit data in each MLC cell into separate readable groups. This allows the system to read specific data groups using a single sensing operation, achieving SLC-like read latency while maintaining MLC's higher storage density. The segmented approach enables selective reading without requiring the lower density of SLC memory
Solution Approach 2:
The patent changes the operational parameters of MLC memory by implementing specific encoding and decoding schemes that allow single-sensing operations. By modifying how data is organized and sensed in MLC cells, the system achieves performance characteristics similar to SLC memory while retaining the higher storage density of MLC technology
Data Source
AI summary
Data storage devices and methods to encode and decode data using divisions of memory cell states are disclosed. A method includes dividing data bits into disjoint multiple groups of data bits and storing the data bits into a plurality of memory cells. The storing is done by setting each of the plurality of memory cells to a corresponding state selected from at least three ordered states. For each of the multiple groups of data bits, when a request is received for reading a particular group of the data bits, the request is serviced by selecting a disjoint division of the at least three ordered states of the memory cells into a first set of states and a second set of states. Each of the states in the first set of states has a higher position than any of the states in the second set of states according to the order of the states. For each cell of the plurality of memory cells, a determination is made whether the cell is in the first set of states or the second set of states. Based on the determination, the particular group of the data bits is generated in response to the request for reading the particular group of the data bits without use of additional data that depends upon a state of one of the memory cells.


