Multi-Level Memory Cell State Set Assignment for Error Distribution
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Solution Overview
Problem
Conventional multi-level cell (MLC) memory systems face higher read failure rates due to varying error statistics across pages, leading to uncorrected errors or increased complexity and cost when using a common error correction coding (ECC) system.
Innovation Solution
The system distributes bit error rates equally between pages by using multiple state sets with different assignments of data sequences to voltage states, allowing the application of the same ECC code to each page, thereby reducing system complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common ECC system is used for all pages in MLC memory, then system complexity is reduced, but read failure rates increase due to varying error statistics across pages
Solution Approach 1:
The patent applies local quality by assigning different state sets to different pages based on their specific error characteristics. Each page uses a state set optimized for its error statistics, allowing tailored error correction for each page rather than using a uniform approach across all pages.
Solution Approach 2:
The patent changes the parameter of state set assignment across different pages. By varying the state set configuration for each page according to its error profile, the system optimizes error correction performance for each page while maintaining overall system manageability.
2Reliability
If multiple state sets with different data sequence assignments are used to equalize bit error rates across pages, then data reliability improves, but system complexity increases
Solution Approach 1:
Different state sets are assigned to different pages based on their specific error characteristics, allowing each page to benefit from a state set optimized for its local error profile rather than using a uniform state set across all pages.
Solution Approach 2:
The system performs preliminary analysis of error statistics for each page and pre-assigns appropriate state sets before actual data storage. This preliminary characterization allows the system to optimize error correction for each page in advance, improving reliability without adding complexity during operation.
3Manufacturing precision
If state sets are optimized for specific pages based on error statistics, then bit error rates decrease, but manufacturing and operational complexity increases
Solution Approach 1:
The patent changes the state set parameters for different pages based on measured error statistics. By adjusting which state set is assigned to which page, the system achieves optimized error rates without requiring physical manufacturing changes, making the solution easier to implement.
Solution Approach 2:
The system uses feedback from error statistics measurement to determine appropriate state set assignments for each page. This feedback mechanism allows the system to automatically optimize error correction performance based on actual operating conditions without requiring complex manual configuration.
Data Source
AI summary
A system including a state set module to arrange states of a memory cell in three sets. The memory cell stores three bits when programmed to a state. Each set includes three rows of bits. In a set, a row includes one of the three bits of the states. The first, second, and third rows of the first, second, and third sets include a first number of state transitions. The second, third, and first rows of the first, second, and third sets include a second number of state transitions. The third, first, and second rows of the first, second, and third sets include a third number of state transitions. A write module writes first, second, and third portions of data to a plurality of memory cells, each memory cell storing the three bits when programmed to a state, using states selected respectively from the first, second, and third sets.