Multi-Pass Memory Cell Programming for Faster QLC State Verification
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Solution Overview
Problem
As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, planar memory cells face challenges due to process technology limitations and reliability issues, and programming and reading multi-level memory cells become inefficient and less accurate with increased bits per cell.
Innovation Solution
A method for programming memory cells involves performing a first program operation to achieve N different states, followed by a second program operation to achieve k states within those N groups, with grouping based on coupling offsets and using specific verification voltages to ensure accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in each memory cell is increased to increase storage capacity, then storage density is improved, but programming time increases and read margin is reduced
Solution Approach 1:
The programming process is divided into multiple passes, with each pass programming a subset of memory cells to specific intermediate states. This segmentation allows parallel processing of different cell groups, reducing overall programming time while achieving high storage capacity through multi-level cells
Solution Approach 2:
Memory cells are pre-programmed to intermediate states in the first pass before final programming. This preliminary action enables more efficient final programming in the second pass, reducing total programming time while maintaining accurate read margins through controlled state transitions
2Quantity of substance
If the number of bits stored in each memory cell is increased to increase storage capacity, then storage density is improved, but read margin is reduced
Solution Approach 1:
The state space of multi-level cells is segmented into intermediate states and final states. This segmentation allows verification at intermediate states with appropriate margins, preventing cumulative errors and maintaining read margin accuracy even as total storage capacity increases through multiple bits per cell
Solution Approach 2:
Verification operations are performed after each programming pass to detect and correct programming errors. This feedback mechanism ensures that read margins are maintained by identifying cells that have not reached their target states and re-programming them, thereby preserving measurement precision despite increased storage capacity
3Device complexity
If a single program operation is used to program memory cells to all target states, then device complexity is reduced, but programming efficiency is reduced
Solution Approach 1:
The programming operation is segmented into multiple passes, each targeting specific state ranges. This segmentation increases programming efficiency by allowing optimized programming strategies for different state groups, compensating for the increased operational complexity through systematic organization
Solution Approach 2:
Programming parameters such as voltage levels and pulse durations are changed between passes to optimize for different programming stages. This parameter optimization improves overall programming efficiency despite the multi-pass approach, as each pass uses parameters tuned for its specific state transitions
Data Source
AI summary
The present disclosure provides a programming method, a memory device and a memory system. The method includes, based on coupling offsets, dividing target programmed states into N groups, each group corresponding to a different first programmed state, wherein an i-th group has Ki number of different target programmed states and corresponds to an i-th first programmed state. At least two groups of target programmed states have two different numbers of target programmed states. The method also includes performing a first program operation to program memory cells to respective first programmed states; and performing a second program operation to program an i-th group of memory cells at the i-th first programmed state to Ki number of different target programmed states.