Semiconductor Memory Cell Step Layout for CMP Flatness
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Solution Overview
Problem
In semiconductor manufacturing, the progression to nanometer technology nodes has made it challenging to control the flatness of underlying layers during lithography operations, particularly due to height differences between non-volatile memory cells and peripheral circuits, which affect chemical mechanical polishing (CMP) performance.
Innovation Solution
A manufacturing process involving the formation of a 'step' between non-volatile memory cell and peripheral circuit areas on a substrate, with controlled etching to create a height difference that aligns with the interlayer dielectric layer, and varying gate dielectric layer thicknesses for different voltage circuits to optimize CMP operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing is performed to planarize the underlying layer, then the flatness for lithography operations is improved, but height differences between non-volatile memory cells and peripheral circuits worsen CMP performance
Solution Approach 1:
The substrate surface is segmented into different levels by forming a step structure, where the peripheral circuit area is recessed relative to the non-volatile memory cell area. This segmentation allows different regions to have optimized surface heights for their respective functions, enabling both good flatness for lithography and effective CMP performance by reducing height differences between structural elements.
Solution Approach 2:
Different regions of the substrate are given different surface qualities through the step formation. The peripheral circuit area is locally recessed to create a lower surface level, while the non-volatile memory cell area maintains a higher level. This local differentiation in surface quality optimizes both lithography flatness and CMP performance in respective regions.
2Manufacturing precision
If gate dielectric layer thickness is varied for different voltage circuits, then CMP operation optimization is improved, but device complexity increases
Solution Approach 1:
Gate dielectric layers are formed with different thicknesses in different circuit regions based on voltage requirements. High voltage circuits receive thicker gate dielectric layers while low voltage circuits receive thinner layers. This local quality differentiation optimizes CMP performance for each region while managing device complexity through systematic thickness control.
Solution Approach 2:
The gate dielectric layer thickness parameter is changed according to the voltage requirements of different circuit regions. By adjusting this critical parameter locally, the invention optimizes CMP operations for high voltage and low voltage circuits separately, achieving better overall manufacturing precision without excessive complexity increase.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.