Semiconductor Memory Cell Substrate Impurity Region Erase Control
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Solution Overview
Problem
Semiconductor memory devices with three-dimensional memory cells face challenges in achieving enhanced erase control performance, particularly in structures where the side-connected source structure is costly and may degrade erase control performance due to increased gate-to-drain distance in alternative configurations like the C2C structure.
Innovation Solution
The semiconductor memory device incorporates a cell substrate with a first conductivity type and a second impurity region of higher impurity concentration, which is spaced apart from the first impurity region, to enhance erase control performance by allowing high voltage application for hole supply and electron tunneling during erase operations, thereby improving erase efficiency without relying on costly side-connected source structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a side-connected source structure is used, then erase control performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent introduces a second impurity region with higher impurity concentration than the cell substrate, creating a localized high-concentration region that enhances erase control performance without requiring a complete redesign of the overall structure. This local modification allows achieving better erase control while maintaining cost-effectiveness compared to side-connected source structures.
Solution Approach 2:
The patent changes the impurity concentration parameter by introducing a second impurity region with higher impurity concentration than the cell substrate. This parameter change enables improved erase control performance through enhanced hole supply capability, avoiding the need for costly side-connected source structures while maintaining effective erase operations.
2Device complexity
If the gate-to-drain distance is increased in alternative configurations, then device complexity is reduced, but erase control performance deteriorates
Solution Approach 1:
The patent creates a localized high impurity concentration region (second impurity region) that compensates for the increased gate-to-drain distance in alternative configurations. This local quality enhancement ensures sufficient hole supply for erase operations even when the gate-to-drain distance is increased, maintaining erase control performance without requiring complex side-connected source structures.
Solution Approach 2:
The patent modifies the impurity concentration parameter in a specific region to compensate for the increased gate-to-drain distance. By increasing the impurity concentration in the second impurity region, the patent ensures adequate hole supply for erase operations despite the larger distance, achieving a balance between simplified structure and maintained performance.
3Productivity
If high voltage is applied for hole supply during erase operations, then erase efficiency is improved, but risk of damage increases
Solution Approach 1:
The patent introduces a second impurity region with higher impurity concentration to create a localized region that facilitates hole supply during erase operations. This local enhancement allows for more controlled high voltage application, improving erase efficiency while reducing the risk of damage by concentrating the effect in a specific region rather than across the entire device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances erase control performance in semiconductor memory devices, even in C2C structures, by utilizing the cell substrate as a body for erase operations, leading to improved efficiency and reduced costs compared to GIDL-based methods.
Implementation Method 1
allowing high voltage application for hole supply and electron tunneling during erase operations
Implementation Method 2
allowing high voltage application for hole supply and electron tunneling during erase operations
Data Source
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AI summary
Provided are a memory device, a method of fabricating the same, and an electronic system including the same. The memory device includes a peripheral circuit structure and a cell structure on the peripheral circuit structure. The cell structure comprises a cell substrate including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface and having a first conductivity type, gate electrodes on the first surface of the cell substrate, a channel structure intersecting the gate electrodes and connected to the cell substrate, a first impurity region that is in the cell substrate adjacent to the second surface and has a second conductivity type, and a second impurity region that is in the cell substrate and is spaced apart from the first impurity region, the second impurity region having the first conductivity type with a higher impurity concentration than that of the cell substrate.