Non-volatile Memory Cell With Surrounded Charge Storage
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Solution Overview
Problem
The miniaturization of semiconductor memory devices leads to reduced gaps between unit cells, causing electric charges to affect neighboring cells, and high voltage applied to some cells can arbitrarily change the state of neighboring cells, resulting in operational disturbances.
Innovation Solution
A non-volatile memory cell design featuring a substrate with a first oxide film, source and drain, a charge storage unit (such as carbon nanotubes, fullerene, or nanocrystalline material) surrounded by a second oxide film, and a gate made of polysilicon or metal with a work function of 4.2 eV to 5.1 eV, which minimizes interference between cells by fully surrounding the charge storage unit and reducing the pitch between gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gap between unit cells is reduced to achieve high integration and miniaturization, then device size is reduced, but electric charges stored in unit cells affect neighboring unit cells causing operational disturbances
Solution Approach 1:
The patent divides the memory structure into isolated unit cells surrounded by element isolation units. Each unit cell is segmented and electrically isolated from neighboring cells through the element isolation units, preventing charge interference while maintaining miniaturization. The gate lines are also segmented to connect only adjacent charge storage units within the same unit cell.
Solution Approach 2:
The element isolation units act as intermediary structures between neighboring unit cells. These isolation units physically and electrically separate adjacent cells, serving as a mediator that prevents direct electrical interaction between cells while allowing the overall device to maintain high integration density.
2Power
If high voltage over 10V is applied to gates of some unit cells, then charge storage and retrieval is enabled, but the state of neighboring cells changes arbitrarily causing operational disturbances
Solution Approach 1:
The gate lines are segmented into separate sections for different signal processing lines. Each gate line section is electrically isolated and connects only to charge storage units on the same signal processing line. This segmentation ensures that high voltage applied to one gate line does not affect neighboring cells on different signal processing lines.
Solution Approach 2:
The element isolation units serve as electrical intermediaries that block high voltage interference from propagating to neighboring cells. When high voltage is applied to a gate line, the element isolation units prevent this voltage from affecting adjacent unit cells, allowing high-power operation without cross-cell interference.
3Area of stationary object
If the pitch between gate lines is reduced to increase integration, then device density increases, but interference between neighboring cells increases
Solution Approach 1:
Gate lines are segmented to connect only adjacent charge storage units within the same unit cell, and different gate lines are electrically isolated by element isolation units. This segmentation allows gate lines to be placed closer together (reduced pitch) while maintaining electrical isolation, thereby increasing device density without increasing interference.
Solution Approach 2:
The element isolation units provide localized electrical isolation at specific positions between unit cells. This local quality approach allows the pitch between gate lines to be reduced in regions where isolation is provided, enabling higher integration while maintaining low interference through localized isolation structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design minimizes disturbance phenomena between neighboring cells by isolating charge storage units within the cell array, allowing for high integration and reduced cell size while maintaining reliable operation.
Implementation Method 1
a charge storage unit formed on the first oxide film
Implementation Method 2
a second oxide film configured to surround the charge storage unit and formed on the first oxide film; and a gate formed to surround the second oxide film
Data Source
AI summary
The present invention relates to a non-volatile memory cell and a method of fabricating the same. The non-volatile memory cell according to the present invention comprises a substrate, a first oxide film formed over an active region of the substrate, a source and drain formed within the active region, a charge storage unit formed on the first oxide film, a second oxide film configured to surround the charge storage unit and formed on the first oxide film, and a gate formed to surround the second oxide film. According to the non-volatile memory cell and a cell array including the same in accordance with the present invention, the charge storage unit is fully surrounded by the gate or the gate line, thus a disturbance phenomenon that may occur due to the memory operation of cells formed in other neighboring gate or gate line can be minimized.