Memory Cell Triples for Data Reliability
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Solution Overview
Problem
Semiconductor memory devices face reliability issues due to small scale geometries and low voltage operations, leading to data instability and errors, with existing error correction schemes and redundancy methods increasing power consumption and requiring additional logic circuitry.
Innovation Solution
An integrated circuit design that writes data to at least three memory cells with a shared bit line and common word line signal, allowing for error correction without additional logic by determining the read data value based on the voltage of the shared bit line, which is dependent on the data values stored in the cells, even if one cell holds a complement value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction schemes are implemented in memory devices, then data reliability is improved, but the number of correctable errors is limited to one bit per word
Solution Approach 1:
The patent combines multiple memory instances (triples of memory cells) to store redundant data, merging their outputs through logical OR operations to achieve error correction capability beyond single-bit errors, thereby resolving the limitation of conventional error correction schemes
2Reliability
If multiple memory instances are used to improve reliability, then data stability is enhanced, but power consumption increases significantly
Solution Approach 1:
The patent merges multiple memory instances into a unified structure where triples of memory cells share common bit lines and word lines, allowing redundant storage without proportionally increasing power consumption, as the shared infrastructure reduces overall energy usage compared to fully independent memory instances
3Reliability
If triple redundancy scheme is implemented, then error identification capability is improved, but the quantity of extra logic circuitry increases
Solution Approach 1:
The patent merges the redundancy mechanism with the existing memory array structure, using shared bit lines and word lines across triples of memory cells, thereby achieving error identification capability without adding significant extra logic circuitry beyond the basic memory cell interconnections
4Use of energy by moving object
If read operation is performed at low voltage, then power consumption is reduced, but read-disturb phenomenon occurs causing data changes
Solution Approach 1:
The patent implements a feedback mechanism where the output of the logical OR operation is written back to the memory cells during read operations, compensating for any read-disturb effects and ensuring data integrity is maintained even when reading at low voltages
Data Source
AI summary
An integrated circuit is provided including at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory cells is coupled to one of a plurality of word lines, to control coupling of that row of memory cells to the plurality of bit lines in dependence on a respective word line signal. Word line driver circuitry is configured to group together the word lines of at least three rows of memory calls, such that the word lines of the at least three rows of memory cells share a common word line signal. Thus in a write operation a written data value written into the array of memory cells is written to at least three memory cells having a shared bit line. Read circuitry is coupled to the plurality of bit lines, configured such that in a read operation, in which the at least three memory cells are all coupled to the shared bit line by means of the common word line signal, a read data value is determined in dependence on a voltage of the shared bit line, dependent on data values stored in the at least three memory cells.