Nonvolatile Memory Cell Tunneling Through Different Dielectric Layers
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Solution Overview
Problem
Conventional nonvolatile memory cells face issues with erase disturb and reliability due to the use of additional layers, which increase costs and reduce yield, and the existing single poly process does not adequately prevent data disturbance in unselected memory cells during erasing.
Innovation Solution
The proposed solution involves a novel memory architecture where the orientation of erase lines and programming/erasing methods allow charge carriers to tunnel through different dielectric layers within the memory cell, reducing dielectric failure and data disturbance by maintaining unselected memory cells at voltages closer to each other, thereby improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional nonvolatile memory cells use additional layers (charge storage layer, control gate), then memory functionality is achieved, but manufacturing costs increase, production time increases, and yield decreases
Solution Approach 1:
The patent merges the charge storage function and control gate function into a single integrated structure. The gate electrode serves dual purposes: storing charge (like a floating gate) and controlling current flow (like a control gate). This eliminates the need for separate charge storage layers and control gate layers, reducing device complexity while maintaining memory functionality.
Solution Approach 2:
The gate electrode is designed to perform multiple functions simultaneously: it acts as both a charge storage element and a control element for regulating current flow through the tunnel junction and channel. This multi-functional design reduces the overall number of components needed in the memory cell structure.
2Reliability
If conventional nonvolatile memory cells use additional layers, then memory functionality is achieved, but manufacturing costs increase and production time increases
Solution Approach 1:
By combining multiple functions into a single gate electrode structure, the manufacturing process is simplified and requires fewer process steps. This reduces production time while maintaining the necessary memory functionality that would otherwise require separate layers.
3Reliability
If conventional nonvolatile memory cells use additional layers, then memory functionality is achieved, but yield decreases
Solution Approach 1:
The simplified single gate electrode structure reduces the number of potential failure points in manufacturing. Fewer layers mean fewer alignment criticalities and fewer process steps that could introduce defects, thereby improving yield while maintaining functional integrity.
4Ease of manufacture
If single poly process is used to form gate electrodes, then manufacturing is simplified, but data disturbance in unselected memory cells during erasing cannot be adequately prevented
Solution Approach 1:
The patent introduces local quality variations through different dielectric layer configurations and doping profiles in specific regions of the memory cell. The tunnel junction and channel regions have different electrical characteristics that enable selective erasing of intended cells while protecting unselected cells from data disturbance, even within a single poly process framework.
Solution Approach 2:
The memory cell structure is segmented into distinct functional regions with different electrical properties. The tunnel junction, channel, and gate electrode are designed with different doping concentrations and dielectric characteristics that enable selective control during erasing operations, preventing cross-talk between adjacent cells.
5Device complexity
If charge carriers tunnel through the same dielectric layer during programming and erasing, then process is simplified, but dielectric failure increases
Solution Approach 1:
The dielectric structure is segmented into multiple layers with different functions: one dielectric layer handles charge storage and another handles control. During programming, charge carriers tunnel through one dielectric layer, while during erasing, they tunnel through a different dielectric layer. This segmentation distributes the tunneling stress across different dielectric materials, preventing cumulative damage and failure in any single layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the resistance to erase disturb and improves the reliability of nonvolatile memory arrays by reducing dielectric breakdown and minimizing data disturbance in unselected memory cells during the erasing process.
Implementation Method 1
Programming and erasing are performed by Fowler-Nordheim tunneling
Data Source
AI summary
An electronic device can include a nonvolatile memory cell. In a particular embodiment, during an erase pulse, all unselected lines are at substantially the same voltage, and a row or segment of a row, such as a word, is erased during the erase pulse. In another embodiment, selected control gate and erase lines are at substantially the same voltage during a programming pulse. In a further embodiment, charge carriers tunnel through a dielectric layer of a component during a program pulse, and charge carriers tunnel through a different dielectric layer of a different component during an erase pulse.