Volatile Memory Cell Layout for Soft Error Upset Immunity
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Solution Overview
Problem
Volatile memory elements in integrated circuits are susceptible to soft error upsets caused by cosmic rays and radioactive impurities, leading to data corruption and reliability issues, especially in applications like remote telecommunications equipment, where repairing faulty equipment is burdensome.
Innovation Solution
The integration of memory elements with pairs of address transistors and four transistor pairs, forming inverter-like circuits with distributed inputs, provides immunity to soft error upsets by using n-channel and p-channel transistors connected in series, allowing for effective data write and clear operations while minimizing cross-bar current surges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cross-coupled inverter memory elements are used, then the circuit area is minimized, but the soft error upset immunity is poor
Solution Approach 1:
The memory element is segmented into multiple transistor pairs (first, second, third, and fourth transistor pairs) with distributed inputs from different nodes. This segmentation distributes the radiation strike impact across multiple segments, preventing a single strike from flipping the entire memory state, thus improving soft error upset immunity while maintaining reasonable circuit complexity
Solution Approach 2:
The patent introduces a new dimensional arrangement by connecting transistor pairs in series at output nodes and distributing inputs from multiple nodes (nodes 1, 2, 3, and 4) to different transistor gates. This multi-dimensional connectivity pattern creates redundant signal paths that enhance radiation hardness without substantially increasing area
2Reliability
If more transistor pairs are added to improve soft error immunity, then the reliability increases, but the circuit area increases
Solution Approach 1:
Multiple transistor pairs are merged into a compact configuration where they share common nodes and interconnected structures. The first, second, third, and fourth transistor pairs are combined such that their inputs are distributed from shared nodes, allowing the memory element to achieve enhanced soft error immunity through merged rather than separate implementations, thereby reducing total area
Solution Approach 2:
The transistor pairs serve multiple functions simultaneously: they act as inverter-like circuits for data storage, provide distributed input reception from multiple nodes, and create redundant signal paths for radiation hardness. This multi-functionality allows the same structural elements to address both area constraints and reliability requirements
3Ease of operation
If clear operations are performed to reset memory elements, then the data is cleared, but cross-bar current surges occur
Solution Approach 1:
Before performing clear operations, the patent depowers selected transistor pairs (specifically the second and fourth transistor pairs) to minimize their contribution to cross-bar current. This preliminary depowering action prevents excessive current surges during the subsequent clear operation, allowing safe resetting of memory elements without energy loss from current surges
Data Source
AI summary
Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.