Semiconductor Memory Cell Verification Segmentation
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Solution Overview
Problem
The variability in result values from verify operations in semiconductor devices, particularly in flash memory cells, leads to reduced data storage speed and reliability due to the location of program fail cells, affecting the threshold voltage verification process.
Innovation Solution
A semiconductor device with a memory block configuration that includes even and odd memory cells, where an operation circuit performs separate and simultaneous verify operations based on the number of adjacent program fail cells, optimizing the verify process to improve data storage speed and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single verify operation is performed on all memory cells, then the verify process is simple, but data storage speed and reliability are reduced due to variability in program fail cell locations
Solution Approach 1:
The patent divides the memory block into even memory cells and odd memory cells, performing separate verify operations on each segment. This segmentation allows the verify process to handle program fail cells more efficiently by treating different regions differently, thereby improving data storage speed without significantly increasing overall complexity.
Solution Approach 2:
The patent implements a dynamic verify operation that adapts based on the location and number of program fail cells. The operation circuit selectively performs first verify operations on even memory cells and second verify operations on odd memory cells based on verify result values, creating a flexible and adaptive verification process that optimizes performance.
2Reliability
If separate verify operations are performed on even and odd memory cells, then data storage reliability is improved, but the verify process becomes more complex
Solution Approach 1:
The memory block is segmented into even and odd memory cells with separate verify operations for each segment. This segmentation improves reliability by allowing targeted verification of program fail cells in specific regions, while the complexity increase is managed through systematic organization of the verify process.
Solution Approach 2:
The patent changes the verify operation parameters dynamically based on the detected program fail cell locations. When program fail cells are detected in odd memory cells, the operation circuit adjusts by performing separate verify operations on even and odd cells, optimizing reliability while adapting complexity to actual needs.
3Measurement precision
If verify operations are performed on all memory cells simultaneously, then the verify process is fast, but accuracy is reduced due to program fail cell interference
Solution Approach 1:
By segmenting the verify operation into separate operations for even and odd memory cells, the patent improves measurement precision in detecting program fail cells. The segmentation reduces interference between adjacent cells during verification, allowing more accurate detection while managing time loss through efficient sequential processing.
Solution Approach 2:
The patent performs verify operations selectively based on program fail cell locations. When program fail cells are detected, separate verify operations are performed on affected segments (even or odd memory cells), applying partial action only where needed rather than uniformly across all cells, thereby improving accuracy without excessive time penalty.
4Productivity
If the verify operation is simplified, then processing time is reduced, but data storage performance deteriorates due to program fail cell variability
Solution Approach 1:
The patent implements a dynamic verify operation that adapts its complexity based on program fail cell locations. The operation circuit selectively performs separate verify operations on even and odd memory cells based on verify result values, creating a flexible system that optimizes data storage performance while maintaining reliability through adaptive verification.
Solution Approach 2:
The verify operation parameters are changed dynamically based on detected program fail cells. When program fail cells are detected in specific regions, the operation circuit adjusts the verify strategy by performing separate operations on even or odd memory cells, optimizing performance while maintaining reliability through parameter adaptation.
Data Source
AI summary
A semiconductor device includes a memory block including even memory cells configured to form an even page and odd memory cells configured to form an odd page. The semiconductor device may also include an operation circuit configured to perform a program operation on the even memory cells and the odd memory cells. A first verify operation may separately verify the even memory cells and the odd memory cells, and a second verify operation may simultaneously verify the even memory cells and the odd memory cells. Further, the operation circuit may be configured to selectively perform the first verify operation and the second verify operation depending on a number of adjacent program fail cells in response to a verify result value.