3D Memory Cell Structure With Vertical Air-Gap Bit Line Isolation
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Solution Overview
Problem
Current semiconductor technologies face challenges in increasing memory cell density and reducing parasitic capacitance in three-dimensional memory devices, which are essential for meeting the demands of large capacity and miniaturization in memory devices.
Innovation Solution
The implementation of a semiconductor device with vertically oriented conductive lines and vertical isolation layers featuring air gaps, which are formed by replacing sacrificial materials with air gaps, helps in increasing memory cell density and reducing parasitic capacitance by optimizing the structure and fabrication method of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional three-dimensional memory device structures are used, then memory cell density can be increased through vertical stacking, but parasitic capacitance between adjacent conductive lines increases
Solution Approach 1:
The patent extracts the harmful dielectric material between adjacent bit lines and replaces it with air gaps, effectively removing the source of parasitic capacitance while maintaining the vertical stacked structure for high memory cell density
Solution Approach 2:
The patent introduces air gaps (porous structure) between conductive lines to reduce parasitic capacitance, using the void space instead of solid dielectric material to achieve electrical isolation with minimal capacitive coupling
2Quantity of substance
If vertical stacking of memory cells is implemented, then memory capacity increases, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent segments the device into distinct functional regions with vertical bit lines, word lines, and isolation layers, organizing the complex three-dimensional structure into manageable segments that can be fabricated using standardized processes
Solution Approach 2:
The patent transitions from planar to vertical three-dimensional architecture, stacking memory cells in the vertical dimension to increase capacity while using vertical isolation layers to manage the complexity of the stacked structure
3Quantity of substance
If vertical isolation layers with air gaps are formed by replacing sacrificial materials, then parasitic capacitance is reduced and memory cell density is enhanced, but fabrication process complexity increases
Solution Approach 1:
The patent incorporates sacrificial material layers during the initial stacking process, which are later removed to form air gaps. This preliminary action allows the air gap structure to be created as part of the standard fabrication flow rather than as an additional complex process step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances memory cell density and reduces parasitic capacitance, improving the performance and efficiency of three-dimensional memory devices by allowing for more compact and efficient storage solutions.
Implementation Method 1
reducing parasitic capacitance between the bit lines
Data Source
AI summary
A semiconductor device includes: active layers vertically stacked over a substrate; word lines extending in a direction crossing the active layers over the active layers; a bit line commonly coupled to first sides of the active layers and extending in a direction perpendicular to the substrate; storage nodes of a data storage element that are vertically stacked over the substrate while being coupled to second sides of the active layers, respectively; and vertical isolation layers including air gaps disposed between the bit lines.