Memory Cell With Vertical Trench Control Gate
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Solution Overview
Problem
As memory cells shrink, reducing variations between stored bits becomes a challenge, and existing non-volatile memory technologies struggle to maintain data integrity and reduce errors.
Innovation Solution
A memory cell design featuring a substrate with shallow trench isolations, an active region, a control gate, and an electron trapping stack, where the control gate fills trenches and extends in a different direction, increasing the width of the electron trapping stack and channel width, thereby reducing bit variation and improving data durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced, then storage density is improved, but bit variation increases
Solution Approach 1:
The patent introduces a third dimension by forming trenches vertically into the substrate and filling them with control gate material. This vertical stacking approach increases the effective channel width without expanding the planar footprint, thereby maintaining storage density while reducing bit variation through a larger effective area for charge storage.
Solution Approach 2:
The patent embeds multiple structures within each other: trenches are formed within the substrate, the electron trapping stack is positioned within the tunneling region, and the control gate fills the trenches. This nested arrangement maximizes the use of vertical space to increase the effective channel width without increasing the overall device footprint.
2Quantity of substance
If memory cell size is reduced, then storage density is improved, but data integrity deteriorates
Solution Approach 1:
By transitioning to a three-dimensional structure with vertical trenches and stacked layers, the patent increases the effective area of the electron trapping stack without increasing the planar cell size. This larger effective area improves data integrity by providing more space for charge storage, reducing the impact of variability in smaller devices.
Solution Approach 2:
The patent employs a composite stack structure consisting of multiple dielectric layers (tunneling dielectric, charge storage layer, blocking dielectric) formed in the electron trapping stack. This multi-layer composite structure enhances data integrity by providing distinct functional zones for charge injection, storage, and retention, while maintaining compact dimensions.
3Quantity of substance
If memory cell size is reduced, then storage density is improved, but error rates increase
Solution Approach 1:
The vertical trench structure and stacked layers create a three-dimensional electron trapping stack with increased effective volume. This additional dimensional space reduces error rates by providing a larger target area for charge storage, making the device less susceptible to manufacturing variations and charge loss in scaled-down devices.
Solution Approach 2:
The patent incorporates an electron trapping stack with a multi-layer dielectric structure that acts as a cushion against charge loss and manufacturing variations. The tunneling dielectric, charge storage layer, and blocking dielectric work together to prevent premature charge loss, providing a buffer that reduces error rates even as device dimensions are reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances data integrity by reducing bit variation and error rates while maintaining the electron trapping stack's area density, even as memory cell size decreases, and is compatible with existing fabrication processes.
Implementation Method 1
a thermal process is performed to oxidize the active region exposed through the first STI and the second STI to form a silicon oxide layer
Data Source
AI summary
A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.