Memory Cell Structure to Prevent Insulating Layer Voids
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Solution Overview
Problem
Conventional memory devices suffer from void formation in the insulating layer due to high memory cell density, which degrades performance and reliability.
Innovation Solution
The memory device incorporates memory cells with specific width and height ratios and tapered side surfaces to prevent void formation in the insulating layer, ensuring no voids are formed between adjacent top contact wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell density is increased to improve storage capacity, then productivity is improved, but voids form in the insulating layer degrading reliability
Solution Approach 1:
The patent changes the geometric parameters of the memory cell structure, specifically implementing a tapered side surface profile and controlling the width-to-height ratio of electrodes. The bottom electrode has a greater width than the top electrode, creating a tapered configuration that prevents void formation in the insulating layer during deposition processes, thereby maintaining reliability while enabling higher cell density
2Productivity
If memory cell density is increased to improve storage capacity, then productivity is improved, but structural integrity deteriorates due to void formation
Solution Approach 1:
The patent modifies structural parameters by implementing a tapered side surface profile where the bottom electrode width exceeds the top electrode width. This geometric parameter change ensures proper material flow and adhesion during deposition, preventing void formation and maintaining structural integrity even at high memory cell densities
3Productivity
If memory cell density is increased to improve storage capacity, then productivity is improved, but manufacturing precision is compromised due to void formation
Solution Approach 1:
The patent implements a tapered side surface profile with controlled width-to-height ratios of electrodes. This parameter change optimizes the deposition process by ensuring proper material coverage and adhesion, preventing void formation in the insulating layer and maintaining high manufacturing precision even when producing high-density memory arrays
Data Source
AI summary
A memory device includes a memory cell comprising a bottom electrode, a top electrode, and a dielectric layer interposed between the bottom electrode and the top electrode. The bottom electrode has a first width W1. The top electrode has a top surface that has a second width W2 between two edges of the top surface. The memory cell has a first height H1 extending from a lower surface of the bottom electrode to the top surface of the top electrode. The memory device further includes a top contact wire coupled to the top electrode. The top contact wire has a top surface that has a third width W3, a second height H2 at a location between two adjacent memory cells, and a third height H3 extending between the top surface of the top contact wire and the insulating layer, where W1>W3>W2 and H2>H1>H3.