Memory Cell Voltage Boosting for Writing Margin
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Solution Overview
Problem
As semiconductor process technology nodes advance to smaller dimensions and lower supply voltages, the yield of memory cell operations is compromised due to the need for a lower VDDmin value, leading to increased leakage current and larger memory cell sizes, particularly because the NMOS passgate transistor is designed to be larger than the PMOS pull-up transistor to ensure data writing margin.
Innovation Solution
The memory cell design includes PMOS and NMOS transistors with equal current driving strength, eliminating contention between them, allowing for reduced transistor sizes and minimizing leakage current by ensuring that node ND is set to a low logical value before writing, thereby enabling faster and more efficient data writing operations at lower voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the NMOS passgate transistor size is increased to provide sufficient writing margin, then the writing capability is improved, but the memory cell size increases and leakage current increases
Solution Approach 1:
The patent changes the voltage parameter by applying a boosted write voltage (VW) to the passgate, which is higher than the normal supply voltage VDD. This voltage boost provides sufficient writing margin without requiring an oversized transistor, thus resolving the contradiction between writing capability and cell size
2Reliability
If the NMOS passgate transistor size is increased to provide sufficient writing margin, then the writing capability is improved, but the leakage current increases
Solution Approach 1:
The patent uses voltage boosting to provide temporary high writing strength only when needed, rather than maintaining a permanently large transistor. The passgate transistor can be smaller since it operates at boosted voltage during writes, reducing both size and associated leakage current
3Use of energy by moving object
If the supply voltage VDDmin is lowered to support smaller technology nodes, then the power consumption is reduced, but the writing margin deteriorates
Solution Approach 1:
The patent introduces dynamic voltage boosting during write operations. The passgate receives a temporary voltage boost (VW > VDD) only when writing is needed, allowing the system to operate at low VDD for power efficiency while providing high writing strength temporarily when required
Solution Approach 2:
The patent changes the voltage parameter by applying a boosted write voltage (VW) to the passgate, which is higher than the normal supply voltage VDD. This voltage boost provides sufficient writing margin without requiring an oversized transistor, thus resolving the contradiction between writing capability and cell size
Data Source
AI summary
In a method, various operations are performed based on a voltage line coupled with a plurality of memory cells. Storage nodes of the plurality of memory cells are caused to change to a first logical value. Another first logical value is applied to a plurality of data lines. Each data line of the plurality of data lines carries data for each memory cell of the plurality of memory cells. A control line of the plurality of memory cells is activated. A first voltage value is applied to the voltage line. The first voltage value causes the another first logical value on the plurality of data lines to be transferred to the storage nodes of the plurality of memory cells.