Memory Cell Voltage Compensation for NAND Stability
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Solution Overview
Problem
In highly integrated rewritable non-volatile semiconductor memory devices, the shared word line configuration leads to variations in voltage waveforms applied to memory cells, causing dispersion in threshold voltage shifts, which affects the stability and reliability of the memory device, especially in three-dimensionally structured NAND memory systems.
Innovation Solution
The semiconductor device employs a compensation voltage generating circuit in conjunction with the column control circuit to adjust the bit line voltages based on the resistance value of the word line, differentiating the voltage between gate electrodes and channels in memory cells across different layers to minimize threshold voltage dispersion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a shared word line configuration is used in highly integrated memory devices, then memory cell density is improved, but voltage waveform variation across memory cells increases
Solution Approach 1:
The patent applies local quality by differentiating the potential control strategy based on the spatial location of memory cells relative to the row control circuit. Memory cells are divided into two groups: those closer to the row control circuit and those farther away. Each group receives a differently adjusted bit line potential, creating a localized compensation approach that addresses the position-dependent voltage waveform variation while maintaining the shared word line configuration for high density.
2Quantity of substance
If word line length varies across memory cells, then memory cell capacity increases, but threshold voltage shift dispersion increases
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting the bit line potential parameter based on the selected memory cell's position. The row control circuit modifies the bit line potential to have a first adjusted value for cells closer to the circuit and a second adjusted value for cells farther away. This parameter adjustment compensates for the varying word line lengths and their associated resistance differences, ensuring uniform threshold voltage shift across all memory cells despite their different distances from the control circuit.
3Quantity of substance
If three-dimensional NAND memory structure is used, then integration density is improved, but threshold voltage dispersion in stacking direction increases
Solution Approach 1:
The patent addresses the three-dimensional threshold voltage dispersion by introducing an additional control dimension through bit line potential adjustment. Instead of only controlling word line potentials, the system adds the bit line potential as a second control dimension that can be differentiated based on the vertical stacking position of memory cells. This allows compensation for threshold voltage variations in the stacking direction by applying position-dependent potential adjustments, thereby maintaining threshold voltage uniformity across multiple memory cell layers.
Data Source
AI summary
A semiconductor device includes first and second memory cells, a first word line, and a first and second bit lines, and a row control circuit. The first memory cell has a first gate electrode and a first channel having one end and another end. The second memory cell has a second gate electrode and a second channel having one end and another end. The first word line electrically connected with each of the first gate electrode and the second gate electrode. The first and second bit lines electrically connected with the first and second channels, respectively. When a threshold voltage of each of the first and second memory cells are caused to be shifted, the semiconductor device causes a first voltage between the first gate electrode and the first channel and a second voltage between the second gate electrode and the second channel to be differentiated.