Memory Cell Voltage Control for Leakage Current Reduction
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Solution Overview
Problem
Next-generation memory devices require high integration density, low power consumption, and fast data access, but existing technologies face challenges in achieving these requirements, particularly in maintaining data retention and reducing read errors in multi-level resistive memory cells.
Innovation Solution
The method involves a memory device with memory cells at intersections of signal lines, using a variable resistor and a selection element, where specific voltage levels are applied to selected and non-selected signal lines to minimize leakage currents during write and read operations, ensuring that the voltage difference between inhibition and selection voltages is below the threshold, allowing for efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration density is implemented in memory devices, then storage capacity increases, but leakage current control becomes more difficult and power consumption increases
Solution Approach 1:
The patent applies different voltage levels to different signal lines based on their selection status. Selected signal lines receive voltages that enable data operations, while non-selected signal lines receive inhibition voltages that prevent leakage current. This localized voltage control ensures that only the necessary memory cells and signal lines consume power during operations, thereby maintaining high integration density while controlling overall power consumption and leakage current.
Solution Approach 2:
The patent dynamically changes voltage parameters during write and read operations. During write operations, a first inhibition voltage is applied to non-selected first signal lines while a first set write voltage is applied to the selected first signal line. During read operations, a second inhibition voltage is applied to non-selected first signal lines while a read voltage is applied to the selected bit line. These parameter changes ensure that high integration density is achieved without excessive leakage current, as voltages are optimized for each operational state.
2Speed
If voltage levels are increased to improve write speed, then data access speed increases, but power consumption increases
Solution Approach 1:
The patent applies high voltages only to the selected signal lines that are actively involved in data operations, while applying low inhibition voltages to all other non-selected signal lines. This localized high-voltage application enables fast data access speed in the selected memory cells without causing system-wide power consumption increases. The inhibition voltages on non-selected lines prevent unnecessary power dissipation while maintaining the ability to quickly switch to high-speed operations when needed.
Solution Approach 2:
The patent uses periodic switching between different voltage states for signal lines. During write operations, the selected first signal line receives a high first set write voltage for fast data programming, while during read operations, the selected bit line receives a read voltage. Non-selected lines periodically receive inhibition voltages to minimize power consumption during transitions between operations. This periodic voltage switching enables high data access speed when needed while maintaining low average power consumption.
3Loss of energy
If inhibition voltages are applied to non-selected signal lines, then leakage current is reduced, but voltage control complexity increases
Solution Approach 1:
The patent uses the same inhibition voltage signal for multiple non-selected first signal lines simultaneously during write operations, and the same second inhibition voltage signal for multiple non-selected first signal lines during read operations. This universal inhibition approach reduces leakage current across all non-selected lines without requiring individual voltage control for each line, thereby simplifying the voltage control architecture while effectively minimizing leakage current in high-density memory devices.
Data Source
AI summary
Methods of operating a memory device include; applying a first set write voltage to a selected first signal line connected to a selected memory cell, applying a first inhibition voltage to non-selected first signal lines connected to non-selected memory cells, and controlling a first voltage of a selected second signal line connected to the selected memory cell to be less than the first set write voltage, and a difference between the first inhibition voltage and the first voltage is less than a threshold voltage of the selection element.