Nonvolatile Memory Cell Voltage Distribution Control
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Solution Overview
Problem
Existing semiconductor nonvolatile memory devices face challenges in narrowing the distribution range of cell voltage while preventing writing delays, due to insufficient operation margins.
Innovation Solution
The semiconductor nonvolatile memory device incorporates a plurality of write bit line current or voltage control circuits that control bit line currents to simultaneously perform writing into multiple memory cells, allowing for the adjustment of current levels to narrow the cell voltage distribution range without delaying writing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the rise range of pulse voltage is decreased to narrow the cell voltage distribution range, then the manufacturing precision is improved, but the writing time increases due to insufficient operation margin
Solution Approach 1:
The patent applies local quality by differentiating the writing current for different memory cells based on their individual characteristics. Specifically, it identifies a first memory cell with a smaller write/erase window and provides it with a first writing current, while providing a second writing current to a second memory cell with a larger write/erase window. This localized adaptation allows each cell to receive optimized current levels, narrowing the overall voltage distribution while maintaining appropriate writing speeds for each cell type.
Solution Approach 2:
The patent implements dynamics by making the writing current adjustable and adaptive rather than fixed. The control circuit dynamically selects and switches between different writing current levels based on real-time verification results and cell characteristics. This dynamic adjustment enables the system to optimize the balance between writing speed and voltage distribution narrowing, preventing writing delays while improving precision.
2Productivity
If the writing current is increased to maintain writing speed, then the productivity is improved, but the cell voltage distribution range widens reducing reliability
Solution Approach 1:
The patent applies local quality by differentiating the writing current for different memory cells based on their individual characteristics. Specifically, it identifies a first memory cell with a smaller write/erase window and provides it with a first writing current, while providing a second writing current to a second memory cell with a larger write/erase window. This localized adaptation allows each cell to receive optimized current levels, narrowing the overall voltage distribution while maintaining appropriate writing speeds for each cell type.
Solution Approach 2:
The patent implements feedback by using verification results to guide subsequent writing operations. The control circuit performs verification after writing operations and uses these results to determine whether to continue writing, switch current levels, or adjust the writing strategy. This feedback mechanism ensures that writing speed is maintained when appropriate while preventing excessive current that would widen voltage distribution and reduce reliability.
Data Source
AI summary
A semiconductor nonvolatile memory device or the like capable of narrowing a cell voltage distribution range while suppressing write delay is provided. The semiconductor nonvolatile memory device includes: a plurality of gate lines; a plurality of bit lines intersecting the plurality of gate lines; and a plurality of memory cells connected to respectively intersection points between the gate lines and the bit lines. The plurality of memory cells are connected to one gate line selected from among the plurality of gate lines respectively via the different bit lines, and the semiconductor nonvolatile memory device further includes a plurality of write bit line current or voltage control circuits respectively controlling bit line currents in order to simultaneously perform writing into the plurality of memory cells.