Semiconductor Memory Cell Voltage Mapping for Error Rate Uniformity

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Solution Overview

Problem

Current semiconductor memory devices face challenges in uniformly distributing the reliability of reading operations across different pages due to varying error rates, leading to inefficiencies in data retrieval.

Innovation Solution

The implementation of specific voltage mapping schemes, such as 6-6-6-6-7 mapping, 5-5-7-7-7 mapping, and 4-6-7-7-7 mapping, which assign different numbers of reading operations to each page to balance error rates and improve reliability, along with a data scramble method that randomizes data across pages to prevent charge distribution bias.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional reading operations are used without specific voltage mapping schemes, then the memory device can retrieve data from all pages, but error rates vary significantly across different pages leading to non-uniform reliability

Engineering Contradiction:

Improveuniformity of error rates across pagesVSAvoiddata retrieval efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies parameter changes by implementing specific voltage mapping schemes (6-6-6-6-7, 5-5-7-7-7, 4-6-7-7-7 mapping) that assign different numbers of reading operations to each page based on their error rate characteristics. This changes the operational parameters of the memory system to balance reliability across pages while maintaining overall data retrieval efficiency

Inventive Principle:

Principle #35Parameter changes

2Reliability

If data is stored without scrambling across pages, then the memory device can store 5-bits per cell, but charge distribution bias occurs leading to non-uniform error rates

Engineering Contradiction:

Improveuniformity of error ratesVSAvoiddata storage organization

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the 5-bit data stored in each memory cell into separate pages (first page containing first through third bits, second page containing fourth and fifth bits). This segmentation allows different reading operation schemes to be applied to different pages, balancing error rates while maintaining the high-density storage capability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by implementing data scrambling before storage, which randomizes the charge distribution across pages and prevents bias. This preliminary organization of data ensures uniform error rates without requiring complex hardware modifications

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20240312519A1Semiconductor memory device to hold 5-bits of data per memory cell

Publication Date: 2024.09.19 KIOXIA CORP

AI summary

According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.