Memory Cell Embedded Data via Voltage Offset Encoding
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Solution Overview
Problem
The data capacity of memory sub-systems is limited due to physical constraints such as the number and size of physical blocks and memory cells, restricting the amount of data that can be stored and retrieved.
Innovation Solution
The solution involves generating embedded data in memory cells by organizing them into multiple data groups with alternating voltage offsets, allowing for additional data values to be represented by comparing threshold voltage levels, thereby increasing data capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If physical constraints of memory blocks and cells are maintained, then device simplicity is preserved, but data capacity is limited
Solution Approach 1:
The patent applies dimensionality change by introducing a new dimension of data encoding through voltage offset levels. Instead of only storing data in the presence/absence of voltage (traditional binary), the system adds a second dimension by encoding data in the offset amount of the voltage threshold. This allows each memory cell to represent multiple data values (e.g., 0, 1, 2, 3) based on different offset levels, effectively increasing data capacity without adding more physical cells.
Solution Approach 2:
The patent changes the parameter of voltage threshold offset to encode additional data. By varying the offset parameter of the read voltage relative to the programmed threshold voltage, the system can distinguish between multiple data states in each memory cell. This parameter change approach allows the same physical memory structure to represent more data by exploiting the continuous nature of voltage thresholds rather than discrete presence/absence states.
2Quantity of substance
If voltage offsets are applied to increase data capacity, then data storage capability is improved, but measurement precision requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the voltage threshold range into distinct segments or levels. Each segment corresponds to a specific data value (e.g., thresholds in ranges 0-1V for data '0', 1-2V for data '1', etc.). By segmenting the continuous voltage spectrum into discrete intervals, the system can reliably distinguish between multiple data states even with measurement variations, as long as the measured threshold falls within the appropriate segment range.
Solution Approach 2:
The patent employs beforehand cushioning by designing the voltage offset levels with sufficient margins between them. The offset amounts are chosen to create adequate separation between adjacent data states, providing a cushion against measurement noise and variations. This ensures that even with imperfect measurement precision, the system can reliably distinguish between different data values by maintaining sufficient voltage separation between encoding levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the data capacity of memory sub-systems by enabling the representation of additional data values through voltage offsets between groups of memory cells, enhancing data storage and retrieval capabilities.
Implementation Method 1
applying a first voltage offset to a first set of alternating groups of the multiple groups of memory cells to establish a first data value for the first set of alternating groups; applying a second voltage offset to a second set of alternating groups of the multiple groups of memory cells to establish a second data value for the second set of alternating groups
Data Source
AI summary
A processing device determines a target bit error rate corresponding to a point of a first programming voltage distribution level corresponding to memory cells of a memory sub-system and a second programming voltage distribution corresponding to the memory cells of the memory sub-system. An offset voltage level corresponding to the point at the target bit error rate is selected. A first portion of a first group of the memory cells in the first programming voltage distribution level is programmed at a threshold voltage level to set a first embedded data value. A second portion of a second group of the memory cells in the second programming voltage distribution level is programmed at the threshold voltage level offset by the offset voltage level to set a second embedded data value.