Memory Cell Voltage Overstress Protection via Stacked Transistors
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Solution Overview
Problem
Conventional memory elements in integrated circuits face voltage overstress issues due to the use of elevated positive and lowered ground power supply voltages, leading to potential transistor breakdown and reliability concerns, with thick oxide transistors offering countermeasures that require additional processing steps.
Innovation Solution
The implementation of memory cells with cross-coupled circuits and additional stacked n-channel transistors connected between different power supply lines, where the gates of these transistors are driven to separate voltage levels to reduce voltage stress, and access transistors controlled by address signals for read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If elevated positive and lowered ground power supply voltages are used in memory cells, then pass gate performance is improved and leakage is reduced, but voltage overstress occurs leading to transistor breakdown and reliability issues
Solution Approach 1:
An intermediate voltage supply line is introduced between the elevated positive power supply and the n-channel transistor gates. This intermediate line provides a buffered voltage level that prevents direct exposure to the full elevated voltage stress, thereby protecting the transistors while still enabling improved pass gate performance through controlled voltage enhancement.
Solution Approach 2:
The voltage parameters supplied to the memory cell are dynamically managed through separate control lines. The positive power supply voltage and ground power supply voltage are independently adjustable, allowing optimization of pass gate performance while maintaining transistor safety margins through parameter separation and independent control.
2Reliability
If thick oxide transistors are used to counteract voltage overstress, then transistor breakdown is prevented, but additional processing steps are required
Solution Approach 1:
Instead of changing the physical structure (oxide thickness) of the transistors, the solution changes the electrical parameters (voltage levels) supplied to the memory cell. By using separate positive and ground power supply voltage lines with controlled voltage levels, the same reliability protection is achieved without modifying the transistor fabrication process.
3Ease of manufacture
If standard power supply voltages are used in memory cells, then fabrication is simpler, but pass gate performance is limited and leakage increases
Solution Approach 1:
The power supply system is segmented into separate positive power supply voltage lines and ground power supply voltage lines that can be independently controlled. This segmentation allows standard fabrication processes to be used while enabling optimized voltage levels to be applied specifically to the memory cell, improving pass gate performance without complicating the overall fabrication process.
Data Source
AI summary
Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled inverters. Each of the two cross-coupled inverters may be coupled between first and second power supply lines and may include a transistor with a gate that is connected to a separate power supply line. Another suitable memory cell arrangement may include three cross-coupled circuits. Two of the three circuits may be powered by a first positive power supply line, while the remaining circuit may be powered by a second positive power supply line. These memory cells may be used to provide an elevated positive static control signal and a lowered ground static control signal to a corresponding pass gate. These memory cells may include access transistors and read buffer circuits that are used during read/write operations.