Memory Cell Voltage Range Programming for Storage Density
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Solution Overview
Problem
Traditional solid-state memory devices face inefficiencies in programming and reading multiple bits per cell, requiring multiple operations and leading to increased complexity as more bits are stored, due to their binary signal transmission and discrete bit handling.
Innovation Solution
The memory devices store data as voltage ranges, allowing for simultaneous programming and reading of bit patterns across multiple bits per cell, using a sample and hold circuitry to manage threshold voltages and reduce the need for multiple read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits are stored per cell in traditional solid-state memory, then storage density increases, but the number of programming and reading operations increases, leading to increased device complexity
Solution Approach 1:
The patent combines multiple bit operations into a single unified operation. The memory cell structure integrates multiple storage nodes (first and second storage nodes) within a single cell, allowing multiple bits to be programmed and read simultaneously through one programming operation and one reading operation, rather than requiring separate operations for each bit.
Solution Approach 2:
The memory cell is designed with multi-functionality to handle multiple bits per cell. The same cell structure and operation mechanisms are used to store and retrieve multiple bits of data, making the cell universal in handling various bit configurations without requiring different operation modes or additional specialized components for each bit.
2Quantity of substance
If more bits are stored per cell, then storage capacity increases, but the time required for programming and reading operations increases
Solution Approach 1:
The patent enables continuous useful action by performing multiple bit operations in a single continuous programming and reading cycle. The memory cell structure allows all bits within a cell to be programmed simultaneously in one operation and read simultaneously in one operation, eliminating the sequential time loss that would occur with multiple separate operations.
Solution Approach 2:
Multiple bit programming operations are merged into a single programming operation, and multiple bit reading operations are merged into a single reading operation. This combining of operations reduces the total time required by executing all bit operations concurrently rather than sequentially.
3Device complexity
If traditional binary signal transmission is used, then simplicity is maintained, but storage efficiency decreases when storing multiple bits per cell
Solution Approach 1:
The patent transitions from traditional binary signal transmission to a multi-dimensional voltage-based encoding scheme. Instead of using separate binary signals for each bit, the invention uses different voltage levels or voltage ranges to represent multiple bits simultaneously, adding a dimensional aspect to the signal transmission that enables higher storage efficiency without proportionally increasing complexity.
Solution Approach 2:
The memory system changes the parameter used for signal transmission from simple binary states to voltage levels or voltage ranges. By utilizing analog voltage parameters rather than discrete binary signals, the system can encode multiple bits per cell more efficiently, improving storage productivity while maintaining manageable complexity through the unified voltage-based approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances storage efficiency by allowing complete bit patterns to be programmed and read as a single signal, improving performance as the bits per cell count increases, while maintaining reliability and flexibility in bit capacity levels.
Implementation Method 1
Changes in threshold voltage of the cells, through programming of charge storage or trapping layers or other physical phenomena, determine the data value of each cell.
Implementation Method 2
Changes in threshold voltage of the cells, through programming of charge storage or trapping layers or other physical phenomena, determine the data value of each cell.
Implementation Method 3
using a sample and hold circuitry to manage threshold voltages and reduce the need for multiple read operations.
Data Source
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Figure 3
AI summary
Memory devices (301, 301') adapted to receive and transmit analog data signals (320, 35) representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller (310) and a read/write channel (305) convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability. (Fig. 3)