Variable Resistance Memory Cell Voltage Control for Read Margin
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Solution Overview
Problem
Nonvolatile semiconductor memory devices, such as ReRAM, face challenges in securing a sufficient read margin between the set and reset states of memory cells due to variations in resistance values caused by trapped charges and oxygen defects in the variable resistance element, especially as the memory cell array scales up.
Innovation Solution
A control circuit manages voltage application to memory cells, using a smaller verify read voltage during write operations and a larger read voltage during read operations to ensure the memory cell transitions between set and reset states reliably, thereby maintaining a sufficient read margin by controlling the cell current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single read voltage is used for both verify read operations during write and normal read operations, then the circuit design is simplified, but the read margin becomes insufficient due to resistance value variations in memory cells
Solution Approach 1:
The patent applies dynamics by making the read voltage adjustable rather than fixed. The control circuit dynamically selects between a first read voltage (for verify read operations during write) and a second read voltage (for normal read operations) based on the operation type. This dynamic voltage adjustment allows the system to maintain sufficient read margin during normal reads while enabling reliable write verification, resolving the contradiction between circuit simplicity and read margin adequacy.
2Quantity of substance
If the memory cell array is enlarged to increase capacity, then storage capacity is improved, but variations in resistance values increase making it difficult to secure sufficient read margin
Solution Approach 1:
The patent applies parameter changes by introducing multiple read voltage levels (first read voltage and second read voltage) to compensate for resistance value variations that occur when the memory cell array is enlarged. The control circuit selects the appropriate voltage level based on the operation type, allowing the system to maintain adequate read margin even as capacity increases and resistance variations become more significant.
Data Source
AI summary
A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.