Multi-Level Memory Cell Programming With Channel Voltage Segmentation
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Solution Overview
Problem
Existing flash memory technologies face challenges in efficiently programming and verifying memory cells with multiple channel voltage levels, leading to issues such as overlapping threshold voltage distributions and reduced storage capacity.
Innovation Solution
A memory device and method that utilizes a trim register to define subsets of memory cells and corresponding voltage levels for programming operations, incorporating incremental step pulse programming (ISPP) to accurately set and verify threshold voltages for multi-level cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple channel voltage levels are used to increase storage capacity, then storage density is improved, but threshold voltage distribution overlap increases reducing reliability
Solution Approach 1:
The patent segments the programming process into multiple distinct phases (program phase, verify phase, read phase) with different voltage level configurations. During the program phase, multiple channel voltage levels are applied to program different data states. During the verify phase, a single channel voltage level is used to verify each data state, preventing overlap and improving reliability.
Solution Approach 2:
The patent dynamically adjusts the channel voltage level configuration based on the operational phase. The system transitions from using multiple channel voltage levels during programming to using a single channel voltage level during verification, adapting the voltage structure to the specific operational requirements to maintain both high storage capacity and reliable verification.
2Manufacturing precision
If incremental step pulse programming is used to improve programming precision, then programming accuracy is improved, but programming time increases
Solution Approach 1:
The patent implements periodic programming pulses with incremental voltage steps, where each pulse is followed by a verification step. This periodic application of programming voltage allows precise control over threshold voltage shifts while maintaining efficient programming speed through the structured repetition of program-verify cycles.
3Productivity
If multiple channel voltage levels are applied simultaneously to all memory cells, then programming speed is improved, but verification accuracy decreases due to interference
Solution Approach 1:
The patent applies different channel voltage levels to different subsets of memory cells based on their intended data states. During verification, only the specific subset of cells being verified is activated with the appropriate single channel voltage level, while other cells remain inactive or are held at different voltage levels, eliminating interference and improving verification accuracy.
Data Source
AI summary
Memories might include a controller configured to cause the memory to develop a respective voltage level in a channel of each memory cell of a plurality of subsets of memory cells selected for a programming operation, wherein each of the memory cells is connected to a selected access line of the programming operation, and wherein each of the subsets of memory cells corresponds to a respective voltage level of the plurality of voltage levels in a one-to-one relationship; and to apply a programming voltage level of the programming operation to the selected access line. Each of the memory cells has a respective desired data state of a plurality of possible data states of the programming operation, and the respective desired data states of the memory cells of at least one of the subsets of memory cells includes two or more data states of the plurality of possible data states.