Memory Cell Voltage State Management for Error Reduction

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Solution Overview

Problem

Conventional memory sub-systems face increased error rates and performance degradation due to the transition of memory cells from a transient threshold voltage state to a stable state during data storage operations, requiring additional error control operations that reduce system performance.

Innovation Solution

Performing a read operation on memory cells between programming passes to maintain them in a transient threshold voltage state, which reduces error rates, and using threshold-based operations on proximate memory cells or elapsed time to manage this transition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are allowed to transition to stable threshold voltage state during data storage operations, then data storage capacity is improved, but error rates increase and performance degrades

Engineering Contradiction:
Improvedata storage capacityVSAvoiderror rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies preliminary action by performing a read operation on the memory cell before the second programming pass to prevent the threshold voltage from transitioning to the stable state. This preliminary read operation maintains the memory cell in the transient state, ensuring low error rates during subsequent programming operations while enabling adequate time for data storage operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by monitoring the threshold voltage state of memory cells and dynamically adjusting the timing of read operations accordingly. The controller determines whether a read operation is needed based on the detected voltage state, creating a feedback loop that maintains optimal error rates while maximizing storage capacity utilization.

Inventive Principle:
Principle #23Feedback

2Reliability

If error control operations are performed to correct errors from voltage transitions, then data reliability is improved, but system performance decreases

Engineering Contradiction:
Improvedata reliabilityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent prevents errors before they occur by performing a preliminary read operation that maintains the memory cell in the transient threshold voltage state. This proactive approach eliminates the need for subsequent error control operations, thereby maintaining high system performance while ensuring data reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent converts the potentially harmful voltage transition effect into a benefit by utilizing the read operation's dual purpose: it serves both as a data retrieval operation and as a mechanism to prevent threshold voltage transitions. This transforms what could be a performance-costly error correction need into an efficient preventive measure.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If read operations are performed between programming passes to maintain transient voltage state, then error rates are reduced, but additional operations increase time consumption

Engineering Contradiction:
Improveerror rateVSAvoidoperation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies universality by making the read operation serve multiple functions: it retrieves data for potential host access and simultaneously prevents the threshold voltage from transitioning to the stable state. This multi-functionality eliminates the need for separate error prevention operations, thereby reducing overall time consumption while maintaining low error rates.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The read operation is performed as a preliminary action between programming passes, strategically timed to prevent voltage transitions without adding significant overhead. By positioning this operation at an optimal point in the programming sequence, the patent minimizes time loss while achieving the desired error rate reduction.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11710527B2Mitigating a voltage condition of a memory cell in a memory sub-system
Publication Date: 2023.07.25 MICRON TECHNOLOGY INC
  • US11710527B2 patent drawing
  • US11710527B2 patent drawing
  • US11710527B2 patent drawing

AI summary

A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.