3D Memory Cell Wiring Layout for Lower Resistance and Noise
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased wiring resistance and reliability issues due to fine line effects, particularly in memory cell arrays, which also results in noise and slowed response speed of power supply circuits as the load capacity of plate electrodes increases.
Innovation Solution
Incorporating auxiliary wiring electrically connected to the word line via conductors within the memory cell array and providing the power supply line above the memory cell array, connected to the plate electrode via conductors, to reduce wiring resistance and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the semiconductor device is miniaturized, then the integration density is improved, but the wiring resistance increases and reliability deteriorates
Solution Approach 1:
The patent introduces a third-dimensional conductive structure that extends vertically through the insulating film to connect the first electrode to the first conductive layer. This vertical connection path in the Z-dimension reduces the effective wiring length and resistance, allowing miniaturization in the planar X-Y dimensions while maintaining electrical performance through the added vertical dimension.
Solution Approach 2:
The patent introduces a semiconductor layer as an intermediary conductive element that penetrates the first conductive layer and connects the first electrode to external conductors. This intermediary structure provides an additional conduction path that bypasses the high-resistance fine wiring, mediating the electrical connection between miniaturized components.
2Length of moving object
If the wiring is miniaturized, then the device size is reduced, but the wiring resistance increases
Solution Approach 1:
The patent adds a vertical conduction path through the insulating film that connects the first electrode to the first conductive layer. This three-dimensional connection reduces the effective current path length by providing a direct vertical route rather than requiring long lateral connections through miniaturized wiring, thus reducing resistance while maintaining small device footprint.
Solution Approach 2:
The patent segments the conduction path into multiple sections: the first electrode, the semiconductor layer penetrating the first conductive layer, and the connection to external conductors. This segmentation allows each section to be optimized independently, with the vertical semiconductor pathway providing low-resistance connection while the horizontal wiring remains miniaturized.
3Quantity of substance
If the plate electrode load capacity increases, then the memory capacity is improved, but the power supply circuit response speed slows down and noise increases
Solution Approach 1:
The patent segments the power distribution network into localized regions, with each first electrode connected through its own vertical semiconductor pathway to the first conductive layer. This segmentation isolates the high-capacity plate electrodes from each other electrically, reducing mutual interference and noise while allowing each to operate at high capacity without slowing the overall power supply response.
Solution Approach 2:
The first conductive layer acts as an intermediary power distribution network that receives power through vertical semiconductor connections from multiple first electrodes. This intermediary structure distributes power to high-capacity plate electrodes while buffering them from direct connection to the power supply circuit, reducing noise and maintaining fast response speed.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a semiconductor substrate and a capacitor that includes a first electrode extending in a first direction intersecting the semiconductor substrate and a second electrode facing the first electrode. A first conductive layer is above the capacitor and extends in a second direction. A semiconductor layer penetrates the first conductive layer in the first direction. A first conductor can be above or below the first conductive layer and electrically connected to the first conductive layer. A first insulating film is between the first conductive layer and the semiconductor layer. A second conductive layer extends in the second direction and is electrically connected to the first conductive layer via the first conductor.