Memory Cell Layout With Front- and Back-Side Word Lines
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) have become smaller and more complex, the resistance of conductive lines within these digital devices has changed, affecting operating voltages and overall IC performance.
Innovation Solution
The implementation of a memory cell design that includes specific configurations of transistors and word lines, where the first word line supplies a signal from the front-side of the substrate and the second word line supplies a signal from the back-side, reducing resistance capacitance (RC) loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ICs are made smaller and more complex, then integration density and functionality are improved, but resistance of conductive lines increases affecting operating voltages and performance
Solution Approach 1:
The patent transitions from planar (2D) conductor routing to three-dimensional (3D) vertical stacking, where bit lines and word lines are arranged in different vertical layers. This dimensional change allows conductive paths to be shortened and routed more efficiently through the vertical dimension, reducing RC loading effects while maintaining high integration density.
Solution Approach 2:
The memory cell array is divided into multiple segments with different bit line pairs (first bit line pairs, second bit line pairs) arranged in alternating patterns. This segmentation allows for shorter individual conductor lengths and reduced resistance accumulation, while the segmented structure maintains overall high integration density through efficient space utilization.
2Speed
If conventional memory cell designs are used, then manufacturing simplicity is maintained, but speed and power consumption performance are insufficient
Solution Approach 1:
By implementing vertical 3D stacking of bit lines and word lines in different layers, the patent reduces the horizontal routing distance and RC loading, which directly improves operation speed and reduces power consumption compared to conventional planar designs.
Solution Approach 2:
The patent applies different conductor configurations to different regions: first bit line pairs are coupled to first word lines in certain regions, while second bit line pairs are coupled to second word lines in alternating regions. This local differentiation optimizes performance characteristics in specific areas, achieving faster speed and lower power consumption through region-specific optimization.
Data Source
AI summary
A memory cell includes a first, second, third, and fourth transistor, a first and a second inverter, and a first and second word line. The first inverter is coupled to the first and third transistor. The second inverter is coupled to the first inverter and the first and third transistor. The first word line is configured to supply a first word line signal, is on a first metal layer above a front-side of a substrate, and is coupled to the first and third transistor. The second word line is configured to supply a second word line signal, and is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and is coupled to the second and fourth transistor. At least the first, second, third or fourth transistor are on the front-side of the substrate.