Memory Cell Write Assist Circuit for Voltage Drop Compensation
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Solution Overview
Problem
Memory integrated circuits face a challenge in writing operations due to voltage drop from the near-end to the far-end memory cells, resulting in reduced writing ability for far-end cells, necessitating an effective write assist scheme to maintain data integrity and efficiency.
Innovation Solution
The integration of write-assist bit lines and transistors that connect to bit lines and bit lines complementary to the far-end memory cells during writing operations, ensuring a consistent voltage and improved writing ability by charging or discharging bit lines through these assist lines, while disabling assist mechanisms for near-end cells to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write assist scheme is applied to all memory cells, then writing ability is improved, but power consumption increases
Solution Approach 1:
The patent applies write assist only to far-end memory cells (second group) while excluding near-end memory cells (first group). This local differentiation resolves the contradiction by providing enhanced writing ability only where voltage drop occurs, avoiding unnecessary power consumption for near-end cells that do not require assistance.
Solution Approach 2:
The patent divides the memory cell array into two segments: near-end memory cells connected to first word lines and far-end memory cells connected to second word lines. This segmentation allows selective application of write assist to the far-end segment, improving writing ability where needed while minimizing power consumption.
2Stability of the object's composition
If write assist bit lines are connected to bit lines, then voltage consistency is improved, but device complexity increases
Solution Approach 1:
The patent segments the bit line connections by introducing write assist bit lines that are selectively connected only to far-end memory cells. This segmentation maintains voltage consistency for cells requiring assistance while avoiding unnecessary connections for near-end cells, thus balancing voltage stability with circuit simplicity.
Solution Approach 2:
The patent employs dynamic control of write assist transistor gates to connect or disconnect write assist bit lines based on the target memory cell location. This dynamic switching mechanism provides voltage consistency only when and where needed, reducing overall circuit complexity compared to permanent connections.
Data Source
AI summary
An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written.