Memory Cell Write Current Control for Density and Power
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Solution Overview
Problem
The challenge lies in producing memory devices with increased memory cell density within a given device size while meeting design specifications and cost constraints, particularly in efficiently accessing and storing information in high-density memory arrays.
Innovation Solution
The solution involves a memory device architecture that includes a memory array with access components and storage elements, utilizing phase change materials and ovonic threshold switches to manage voltage and current for read and write operations, allowing for multiple currents to flow during write operations to efficiently store information and reduce device size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased for a given device size, then memory storage capacity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The memory device is divided into multiple memory arrays, with each array containing numerous memory cells arranged in a grid structure. This segmentation allows the high-density storage to be organized into manageable units, reducing overall device complexity while maintaining high memory cell density.
Solution Approach 2:
Memory cells are arranged in a two-dimensional grid structure with rows and columns, allowing density to increase in both horizontal and vertical dimensions. This multi-dimensional arrangement enables high storage capacity without proportionally increasing device footprint or complexity.
2Productivity
If multiple currents are allowed to flow during write operations, then write efficiency is improved, but power consumption increases
Solution Approach 1:
Multiple write currents are applied in a sequential, periodic manner rather than simultaneously. The write control circuit selectively activates different current paths at different time intervals during the write operation, achieving efficient data writing while managing peak power consumption through time-multiplexed current application.
Solution Approach 2:
The write control circuit dynamically adjusts which current paths are active based on the specific write operation requirements. By dynamically enabling or disabling current paths through controlled switching, the system optimizes write efficiency for each operation while adapting power consumption to actual needs rather than maintaining constant high power.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient access and storage of information in high-density memory arrays, reducing device size and cost by allowing multiple currents to flow during write operations, thereby improving memory device performance and efficiency.
Implementation Method 1
utilizing phase change materials and ovonic threshold switches to manage voltage and current for read and write operations
Implementation Method 2
utilizing phase change materials and ovonic threshold switches to manage voltage and current for read and write operations
Data Source
AI summary
Some embodiments include apparatuses and methods having first conductive lines, second conductive lines, a memory array including memory cells, each of the memory cells coupled between one of the first conductive lines and one of the second conductive lines. At least one of such apparatuses and methods can include a module configured to cause a first current from a first current source and a second current from a second current source to flow through a selected memory cell among the memory cells during an operation of storing information in the selected memory cell. Other embodiments including additional apparatuses and methods are described.