8-T Memory Cell Write Stability via Word Line Voltage Boost
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Solution Overview
Problem
Conventional six-transistor (6-T) static memory cells face stability issues due to threshold voltage variations as integrated circuit process dimensions shrink, leading to potential failures in SRAM arrays, while eight-transistor (8-T) cells face challenges with lower power writing operations.
Innovation Solution
The implementation of an 8-T memory cell architecture with a separate read access circuit and write access circuit, where the read word line is activated at a low voltage and deactivated to provide a voltage boost to the write word line during a write operation, enhancing write assist and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If 6-T memory cell architecture is used, then compact structure is achieved, but stability deteriorates due to threshold voltage variations
Solution Approach 1:
The memory cell is segmented into separate read access circuit and write access circuit, each with dedicated transistors. The read circuit includes read access transistors while the write circuit includes write access transistors, allowing independent optimization of each function without interference, thereby improving write stability while maintaining compactness.
Solution Approach 2:
The patent introduces a new dimension by adding a dedicated write word line (WWL) separate from the read word line (RWL). This additional control dimension allows independent timing and voltage control of write operations, enabling write assist mechanisms that boost write voltage without affecting read operations, thus resolving the stability issue.
2Reliability
If 8-T memory cell architecture is used, then write stability is improved, but writing at lower voltages becomes difficult
Solution Approach 1:
The write bit line is precharged to a high voltage state (VDDAR) before the write operation begins. This preliminary action stores energy in the write bit line capacitance, which is then transferred to the storage element during the write pulse, enabling write operations at lower supply voltages while maintaining stability.
Solution Approach 2:
The patent dynamically changes the voltage parameter of the write word line by applying a boosted voltage (VDDAR) during write operations. The write assist mechanism temporarily increases the write bit line voltage above the normal VDD level, providing sufficient drive strength for reliable writing without requiring the entire memory system to operate at higher voltages.
3Reliability
If separate read access circuit is added, then read disturb is eliminated, but device complexity increases
Solution Approach 1:
The separate read access transistors are designed to serve dual purposes: they enable read operations without disturbing the stored data, and they provide write assist by precharging the write bit line. This multi-functionality justifies the additional transistor count by delivering multiple benefits beyond just eliminating read disturb.
Data Source
AI summary
A method is provided for writing to a memory cell having a read access circuit that is separate and isolatable from a write access circuit. The method comprises providing a logic state to be written to the memory cell onto a write bit line coupled to the memory cell through the write access circuit, changing a write word line that controls the write access circuit from a deactivated low voltage state to an activated high voltage state, and changing a read word line that controls the read access circuit from an activated low voltage state to a deactivated high voltage state, wherein the change in voltage on the read word line provides a voltage boost to the voltage on the write word line caused by the electrical coupling between the read word line and the write word line to provide write assist to the memory cell during a write operation.