3D Memory Cells With Dual Control Gates And Dielectric Shields
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Solution Overview
Problem
As memory devices are miniaturized to achieve higher storage density, reduced bias voltages for operations like erasing and programming lead to decreased reliability due to lower gate coupling ratios and increased interference between charge storage structures.
Innovation Solution
A three-dimensional memory device design featuring dual control gates with a high dielectric constant material between the control gates and charge storage structures, and a low dielectric constant material separating adjacent control gates, which increases the gate coupling ratio and reduces interference, allowing for efficient programming and erasing operations at lower voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are reduced in size to achieve higher storage density, then storage capacity increases, but reliability decreases due to reduced bias voltages and lower gate coupling ratios
Solution Approach 1:
The patent transitions from planar memory architecture to three-dimensional vertical architecture. Memory cells are stacked in multiple layers with charge storage structures extending vertically, allowing higher storage density without proportionally reducing the active area. This dimensional change maintains sufficient gate coupling ratios even as device density increases.
Solution Approach 2:
The patent employs composite dielectric materials with different dielectric constants in specific layers. High dielectric constant materials are used between control gates and charge storage structures to enhance coupling, while low dielectric constant materials separate adjacent control gates to reduce interference. This composite approach optimizes both coupling and isolation simultaneously.
2Use of energy by moving object
If bias voltages are reduced for miniaturized memory operations, then power consumption decreases, but programming and erasing reliability deteriorates
Solution Approach 1:
The patent modifies the dielectric constant parameter of materials in different regions. High dielectric constant materials near charge storage structures amplify the effect of applied voltages, enabling effective programming and erasing at lower voltages. Low dielectric constant materials in separation regions minimize parasitic coupling, maintaining signal integrity at reduced voltage levels.
Solution Approach 2:
Different dielectric materials with optimized properties are placed in specific locations: high dielectric constant materials where strong coupling is needed, and low dielectric constant materials where interference reduction is critical. This localized optimization allows low-voltage operation without sacrificing reliability.
3Quantity of substance
If control gates are placed closer together to increase density, then storage capacity increases, but interference between adjacent control gates increases
Solution Approach 1:
Low dielectric constant materials are introduced as intermediary layers between adjacent control gates. These materials act as electrical isolators with low parasitic capacitance, preventing interference between closely spaced control gates while allowing the gates to be positioned close together for high density.
Solution Approach 2:
The patent uses uniform low dielectric constant material properties throughout the separation regions between control gates, ensuring consistent isolation characteristics across the entire memory array. This homogeneous approach simplifies manufacturing and ensures predictable interference reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the reliability of memory devices by maintaining high gate coupling ratios and reducing voltage requirements, thereby improving the efficiency and stability of memory operations while minimizing interference between adjacent memory cells.
Implementation Method 1
a high dielectric constant material between the control gates and charge storage structures
Implementation Method 2
a low dielectric constant material separating adjacent control gates
Data Source
AI summary
Various embodiments comprise apparatuses having a number of memory cells. In one such apparatus, each cell has a plurality of control gates. For example, each of two control gates is adjacent a respective side of a charge storage structure. In another apparatus, each cell has a control gate and a shield, such as where the control gate is adjacent one side of a charge storage structure and the shield is adjacent another side of the charge storage structure. Additional apparatuses and methods are described.