Memory Certificate Exchange for Secure Host Access and ECC Control
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Solution Overview
Problem
Existing memory systems face challenges in balancing memory throughput, power consumption, and reliability, with DDR memory providing high bandwidth but high power consumption and LPDDR memory lacking robust RAS capabilities, and memory communication being vulnerable to hacking and unauthorized access.
Innovation Solution
Establishing a trusted communication channel between the memory and host using certificate exchange and secure keys, enabling secure access to system data storage arrays and flexible memory subsystem operations, including secure mode register access and ECC functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DDR memory is used to provide high bandwidth, then memory throughput is improved, but power consumption increases significantly
Solution Approach 1:
The patent changes the operating parameters of the memory subsystem by implementing adaptive frequency adjustment and dynamic voltage scaling. The memory controller dynamically adjusts the memory bus frequency and voltage based on system requirements, allowing the system to operate at lower frequencies (reducing power consumption) when maximum throughput is not required, while being able to scale up to higher frequencies when needed.
Solution Approach 2:
The patent introduces dynamic characteristics to the memory subsystem through adaptive frequency adjustment and dynamic voltage scaling. The system transitions from static, fixed-frequency operation to dynamic operation where frequency and voltage can be adjusted in real-time based on workload requirements, enabling the system to optimize between power consumption and throughput performance.
2Productivity
If memory bus speed is increased to improve memory throughput, then data transfer rate is improved, but bit error rate increases
Solution Approach 1:
The patent implements preliminary error detection and correction mechanisms before data errors can affect system operation. The system performs error checking and correction codes (ECC) validation in advance, and the memory controller is configured to detect and correct bit errors before they propagate through the system, allowing the use of higher bus speeds with maintained reliability.
Solution Approach 2:
The patent implements feedback mechanisms where the memory controller continuously monitors error rates and system performance. When error rates increase at higher speeds, the feedback system automatically adjusts operating parameters such as frequency and voltage to optimal levels that maintain reliability while maximizing throughput performance.
3Use of energy by moving object
If LPDDR memory is used to reduce power consumption, then power usage is improved, but RAS capabilities are compromised
Solution Approach 1:
The patent merges the low power characteristics of LPDDR memory with enhanced RAS capabilities by combining multiple error correction mechanisms. The system integrates on-die ECC, host-side ECC, and error detection and correction codes (ECC) into a unified error protection architecture that works together to provide robust RAS capabilities while maintaining the low power consumption benefits of LPDDR memory.
Solution Approach 2:
The patent creates a composite error correction system that combines multiple error protection technologies working together. This composite approach includes on-die ECC, host-side ECC, and additional error detection and correction codes (ECC), creating a multi-layered protection system that enhances RAS capabilities while preserving the low power characteristics of LPDDR memory.
4Ease of operation
If memory communication is made accessible through standard interfaces, then ease of operation is improved, but security vulnerability increases
Solution Approach 1:
The patent introduces an intermediary security layer in the form of a memory controller that acts as a mediator between the host and the memory subsystem. This intermediary controller implements certificate-based authentication and secure key exchange mechanisms that verify the identity and authorization of accessing components, allowing standard interface accessibility while preventing unauthorized access and hacking attempts.
Solution Approach 2:
The patent performs preliminary security authentication and certificate verification before allowing any memory access operations. The system exchanges secure keys and validates certificates in advance, establishing a trusted communication channel before data transfer begins, thereby preventing security vulnerabilities while maintaining operational accessibility through standard interfaces.
Data Source
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AI summary
A memory subsystem allows the memory controller and the memory to create a trusted communication channel based on a certificate exchange. The memory and memory controller have a key storage to store the certificates. The memory controller can be restricted to only be enabled to access a system data storage array after the trusted communication channel is established.