3D Memory Channel Structure With Barrier Layer for Reliability
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Solution Overview
Problem
Current three-dimensional nonvolatile memory devices face challenges in improving operational reliability and manufacturing efficiency due to limitations in their structural design and manufacturing processes.
Innovation Solution
A semiconductor memory device with a gate stack and channel structure, including a channel layer with a first portion penetrating the gate stack and a second portion protruding higher than the gate stack, a core insulating layer, and a barrier layer between the channel layer and the core insulating layer, along with a method of manufacturing that involves forming these components and implanting conductive impurities into the channel layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional 3D nonvolatile memory device structure is used, then the device can store data in three dimensions, but the operational reliability is insufficient
Solution Approach 1:
The channel layer is segmented into two distinct portions: a first portion that penetrates the gate stack and a second portion that protrudes higher than the gate stack. This segmentation allows different regions of the channel layer to serve different functional purposes, improving operational reliability through better charge control and tunneling characteristics while maintaining a manageable structural complexity through systematic division of functions.
Solution Approach 2:
Different portions of the channel layer are given different local qualities and functions. The first portion penetrating the gate stack is optimized for charge injection and extraction, while the second portion protruding above the gate stack is optimized for charge storage and control. The barrier layer and core insulating layer are strategically positioned to provide localized electrical isolation and field control, enhancing overall device reliability without requiring complete structural redesign.
2Ease of manufacture
If the channel layer penetrates the gate stack completely, then the manufacturing process becomes simpler, but the structural stability deteriorates
Solution Approach 1:
The channel layer is divided into two portions with distinct functions and positions. The first portion penetrates the gate stack to enable charge injection, while the second portion protrudes above the gate stack to provide structural support and additional control. This segmentation allows the manufacturing process to follow a straightforward sequence (forming channel layer, forming gate stack, removing substrate) while the resulting dual-portion structure maintains excellent structural stability through proper distribution of mechanical and electrical functions.
3Reliability
If conductive impurities are implanted into the channel layer, then the electrical performance is improved, but the manufacturing complexity increases
Solution Approach 1:
Conductive impurities are implanted into the channel layer at a predetermined stage in the manufacturing process, before final device assembly and testing. This preliminary action ensures that the channel layer has the required electrical conductivity for optimal performance while allowing subsequent manufacturing steps to focus on structural completion and quality verification, thereby managing overall manufacturing complexity through proper process sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the operational reliability and simplifies the manufacturing process of semiconductor memory devices, improving their structural stability and performance.
Implementation Method 1
a barrier layer disposed between the channel layer and the core insulating layer
Implementation Method 2
implanting a conductive impurity into the second portion of the channel layer
Data Source
AI summary
Provided herein may be a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a gate stack, and a channel structure disposed in the gate stack, wherein the channel structure may include a channel layer including a first portion penetrating the gate stack and a second portion extending from the first portion to protrude higher than the gate stack, a core insulating layer disposed in a central region of the channel structure, and a barrier layer disposed between the channel layer and the core insulating layer.