Memory Device Channel Boosting for Read Speed
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Solution Overview
Problem
Current memory devices face limitations in read and verify operation speeds, particularly as they approach physical scaling limits, necessitating improved methods to enhance operational efficiency.
Innovation Solution
The proposed solution involves a memory device with multiple memory blocks and peripheral circuits that manage select transistors, channel voltages, and voltage applications to optimize read and verify operations, including channel floating and voltage adjustments to speed up channel boosting, thereby reducing operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional read and verify operations are performed in memory devices approaching physical scaling limits, then the memory device structure is maintained, but the operation speed is limited and cannot be sufficiently improved
Solution Approach 1:
The patent applies preliminary action by performing channel boosting operations before the actual read or verify operations. Specifically, the method includes: (1) applying a first voltage to bit lines, (2) applying a second voltage to word lines to boost channel potential, and (3) then performing the read or verify operation. This preliminary channel boosting prepares the memory cell channels in advance, reducing the time required during the actual read/verify operation and thereby improving overall operation speed.
2Quantity of substance
If memory devices use vertically stacked memory cells to overcome physical scaling limits, then storage capacity is improved, but read and verify operation speeds remain relatively low
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting voltage parameters during the read and verify operations. The method involves applying specific voltage levels to bit lines (first voltage) and word lines (second voltage) at different stages of the operation. By optimizing these voltage parameters, particularly through the channel boosting technique where a second voltage is applied to word lines to increase channel potential before reading, the patent improves carrier injection efficiency and reduces operation time, thereby increasing read and verify speeds in vertically stacked memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the operating speed of memory devices by streamlining the read and verify processes, specifically reducing the time required for these operations.
Implementation Method 1
applying a first voltage to bit lines coupled to the memory cells and applying a second voltage to word lines coupled to the memory cells
Data Source
AI summary
Provided herein are a memory device and an operating method thereof. The memory device may include a plurality of memory blocks and one or more peripheral circuits. Each of the plurality of memory blocks may include a plurality of cell strings. The one or more peripheral circuits may perform one or more operations on the plurality of memory blocks. The operations may include turning off select transistors of the cell strings included in the memory blocks, increasing channel voltages of the cell strings included in the memory blocks, turning on, among select transistors included in the memory blocks, select transistors included in a selected memory block, and performing a read or a verify operation on the selected memory block.