Non-volatile Memory Channel Boosting Control for Read Disturb Mitigation

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Solution Overview

Problem

In 3D stacked non-volatile memory devices, channel boosting to prevent read disturbs can lead to hot electron injection, which slows down the read process and is not uniformly necessary for all memory cells, necessitating customized interruption based on cell position to minimize performance issues.

Innovation Solution

Implementing control circuits that apply signals for channel boosting of unselected memory cells, temporarily mitigating boosting based on the position of selected memory cells during read operations, allowing for customized interruption to reduce hot electron injection and maintain performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If channel boosting is applied to unselected memory cells to prevent read disturbs, then read disturb suppression is improved, but hot electron injection occurs which slows down the read process

Engineering Contradiction:
Improveread disturb suppressionVSAvoidread process speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies different boosting strategies to different memory cells based on their position. Specifically, unselected memory cells in certain word line regions receive channel boosting while others do not, creating localized quality differences that prevent hot electron injection in susceptible regions while maintaining read disturb suppression where needed.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the memory array into different regions (e.g., first and second regions of word lines) and applies different boosting policies to each segment. This segmentation allows the system to suppress hot electron injection in regions where it is problematic while maintaining adequate read disturb suppression in other regions.

Inventive Principle:
Principle #1Segmentation

2Object-affected harmful factors

If channel boosting is temporarily interrupted to mitigate hot electron injection, then hot electron injection disturb is reduced, but read process speed is slowed down

Engineering Contradiction:
Improvehot electron injection disturbVSAvoidread process speed
Core Design Contradiction:
Object-affected harmful factorsVSSpeed

Solution Approach 1:

The patent selectively interrupts channel boosting only for unselected memory cells in specific word line regions where hot electron injection is most problematic, rather than uniformly interrupting boosting across the entire memory array. This localized approach minimizes the impact on read speed while still mitigating hot electron injection disturbs.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent dynamically adjusts the channel boosting signal based on the read operation progress and memory cell position. The boosting is temporarily interrupted at specific timing moments during the read process, creating a dynamic control strategy that balances hot electron injection mitigation with read speed maintenance.

Inventive Principle:
Principle #15Dynamics

3Object-affected harmful factors

If uniform channel boosting interruption is applied to all memory cells, then hot electron injection is mitigated, but performance is unnecessarily reduced

Engineering Contradiction:
Improvehot electron injectionVSAvoidread operation performance
Core Design Contradiction:
Object-affected harmful factorsVSProductivity

Solution Approach 1:

The patent implements position-dependent boosting control where unselected memory cells are categorized into different groups based on their word line position. Cells in the first region have boosting interrupted while cells in the second region maintain boosting, creating local quality differences that optimize both hot electron injection mitigation and read performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies partial action by interrupting channel boosting only for a subset of unselected memory cells (those in the first region) rather than all unselected cells. This partial application of the interruption strategy reduces hot electron injection sufficiently while avoiding the excessive performance penalty that would result from universal interruption.

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively mitigates hot electron injection disturbs while optimizing read process speed by tailoring the interruption duration based on the position of memory cells, ensuring efficient data retrieval without unnecessary slowing.

Implementation Method 1

provides an optimum level of channel boosting for unselected memory strings in order to repress both normal and weak-erase types of read disturbs

Methodology Applied
Scientific EffectChannel boosting:

Implementation Method 2

reducing read disturb due to hot electron injection in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages

Methodology Applied
Scientific EffectHot electron injection:

Data Source

PatentEP3420555B1Non-volatile memory with customized control of injection type of disturb during read operations
Publication Date: 2020.12.02 SANDISK TECHNOLOGIES LLC
  • EP3420555B1 patent drawingFigure 1~2
  • EP3420555B1 patent drawingFigure 3
  • EP3420555B1 patent drawingFigure 4

AI summary

A non-volatile memory system includes one or more control circuits configured to read memory cells. The reading of the programmed memory cells includes applying one or more voltages to perform boosting of a channel region associated with unselected memory cells, allowing the boosting of the channel region for a portion of time while applying the one or more voltages, preventing/interrupting the boosting of the channel region while applying the one or more voltages for a duration of time based on position of a memory cell selected for verification, applying a compare signal to the memory cell selected for reading, and performing a sensing operation for the memory cell selected for reading in response to the compare signal.