Memory Channel Controller Segmentation for Data-Type-Based Bus Use
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Solution Overview
Problem
Existing memory systems waste bandwidth and power due to dedicating the full capacity of the memory bus for access requests that require only a portion of its width, leading to inefficient execution of smaller data transfers.
Innovation Solution
Implementing multiple channel controllers that operate independently or in parallel, channelizing data storage and access across multiple memory devices, allowing for parallel execution of smaller access requests and optimizing bus utilization based on data type and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the full capacity of the memory bus is dedicated for each access request, then the access request can be executed with guaranteed bandwidth, but bandwidth is wasted when the data transfer size is smaller than the bus width
Solution Approach 1:
The memory bus is segmented into multiple independent channels (e.g., 4 channels of 16-bit width each forming a 64-bit bus). Each channel can be independently activated based on the data transfer size requirement, allowing the system to use only the necessary channel capacity for each access request rather than always dedicating the full bus width.
Solution Approach 2:
Instead of always activating all memory channels for every access request, the system activates only the partial number of channels needed based on the data size. For small data transfers, only one or a few channels are activated, avoiding the excessive action of using the full bus capacity and thereby reducing power consumption.
2Loss of time
If multiple memory channels are used for parallel execution, then latency is reduced, but device complexity increases
Solution Approach 1:
The memory controller is segmented into multiple independent channel controllers (e.g., four 16-bit channel controllers for a 64-bit bus). Each channel controller can independently execute access requests in parallel, reducing overall access latency while maintaining manageable complexity through modular design.
Solution Approach 2:
Each channel controller is designed with universal functionality to handle different data types (L2P, PMR, CMB) and access patterns. This multi-functionality allows the same channel controller architecture to be reused across multiple channels, reducing overall system complexity despite the increased number of parallel execution units.
3Loss of energy
If the memory bus width is reduced to match smaller data transfers, then power consumption is reduced, but bandwidth utilization is inefficient
Solution Approach 1:
The memory bus operates dynamically by activating different numbers of channels based on the data transfer size requirement. The system can switch between using one channel for small transfers and multiple channels for larger transfers, optimizing the balance between power consumption and bandwidth utilization for each specific access request.
Solution Approach 2:
The effective bus width parameter is changed dynamically based on the access request size. Instead of a fixed bus width, the system adjusts the number of active channels (and thus the effective width) to match the data transfer requirements, improving both power efficiency and bandwidth utilization.
Data Source
AI summary
The present disclosure includes systems, apparatuses, and methods related to memory channel controller operation. For example, a data type associated with an access request may be determined. The access request may be executed by utilizing, responsive to determining the access request is associated with a first data type, a first memory channel controller coupled to a first memory device to access a first memory address range, associated with the first data type, allocated to the first memory device. The access request may be executed by utilizing, responsive to determining the access request is associated with a second data type, the first memory channel controller and a second memory channel controller coupled to a second memory device to access a second memory address range, associated with the second data type, allocated among the first memory device and the second memory device.