Parallel Memory Channel Calibration via Identifier Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In electronic devices, especially mobile devices with finite energy sources, memory channel calibration during boot can lead to incorrect results or system failure due to voltage droop from low battery charge, as existing methods attempt to calibrate all channels in parallel without considering the available energy state.
Innovation Solution
A system where a memory controller is programmable with identifiers for memory channels, allowing only a subset of channels to be calibrated in parallel based on the current charge state of the energy source, ensuring accurate calibration and proper system initialization by matching the number of parallel calibrations to the available energy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all memory channels are calibrated in parallel during boot, then calibration speed is improved, but voltage stability deteriorates due to excessive power consumption from the battery
Solution Approach 1:
The patent segments the memory channels into multiple groups, where each group is calibrated in a separate phase. The memory controller divides the plurality of memory channels into first plurality of groups and second plurality of groups, calibrating channels in the first groups during a first phase and channels in the second groups during a second phase. This segmentation reduces the number of channels calibrated simultaneously, thereby reducing power consumption and preventing voltage droop while still achieving comprehensive calibration across all channels.
Solution Approach 2:
The patent implements dynamic phase adjustment based on voltage monitoring. The memory controller monitors voltage levels during calibration phases and dynamically adjusts the number of channels calibrated in each phase. When voltage drops below a threshold, the controller reduces the number of active calibration channels or extends the duration of lower-phase calibrations. This dynamic adaptation ensures voltage stability is maintained while optimizing calibration throughput based on real-time power availability.
2Loss of time
If multiple memory channels are calibrated simultaneously, then boot time is reduced, but calibration accuracy deteriorates due to power distribution issues
Solution Approach 1:
By segmenting channels into multiple groups calibrated in sequential phases, the patent ensures that each calibration phase operates with sufficient power availability. This segmentation prevents power distribution issues that would otherwise degrade calibration accuracy, while the overlapping and pipelined execution of phases across different memory controllers minimizes the total time impact on boot sequence.
Solution Approach 2:
The patent performs preliminary voltage monitoring and phase planning before initiating calibration. The system assesses voltage levels and prepares the calibration schedule in advance, ensuring that high-precision calibration phases are scheduled when voltage is expected to be stable. This preliminary action ensures calibration accuracy is maintained while optimizing the overall boot time through pre-planned parallel execution where safe.
3Reliability
If all channels undergo calibration during boot, then memory reliability is improved, but energy consumption increases causing voltage droop
Solution Approach 1:
The patent segments the calibration process into multiple phases with different energy consumption levels. First-phase calibration of certain channel groups consumes less power and is performed when voltage is monitored to be in a lower range. Second-phase calibration of remaining channels consumes more power and is performed when voltage conditions permit. This segmented approach ensures all channels receive necessary calibration for reliable operation while distributing energy consumption to prevent voltage droop.
Solution Approach 2:
The patent implements periodic voltage monitoring during the calibration process. The memory controller periodically checks voltage levels and adjusts the calibration schedule accordingly, pausing or reducing calibration activities when voltage drops below thresholds and resuming when voltage recovers. This periodic action ensures memory reliability is maintained through complete calibration while adapting energy consumption to available power, preventing voltage droop-induced failures.
Data Source
AI summary
In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.