3D Memory Channel Cap Structures for Electrical Contact
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional memory devices face challenges in forming effective channel cap structures that provide reliable electrical contact and efficient memory operations, particularly in the formation of semiconductor structures with vertical semiconductor channels and backside semiconductor cap structures.
Innovation Solution
The solution involves forming an alternating stack of insulating and electrically conductive layers, creating memory openings with memory films and vertical semiconductor channels, and selectively growing Group IV-containing material portions to form channel cap structures that contact the vertical semiconductor channels, along with forming source and backside semiconductor cap structures to ensure reliable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory device structures are used, then device complexity is reduced, but electrical contact reliability and memory operation efficiency deteriorate
Solution Approach 1:
The channel cap structure is segmented into multiple functional layers: a first channel cap layer formed at the bottom of the core cavity, and a second channel cap layer formed over the first layer. This segmentation allows each layer to serve specific functions - the first layer provides initial contact with the vertical semiconductor channel, while the second layer enhances the contact area and provides additional electrical pathways, thereby improving electrical contact reliability without requiring complete structural redesign
Solution Approach 2:
The patent transitions from conventional planar contact structures to a three-dimensional stacked configuration. The alternating stack of insulating layers and electrically conductive layers creates vertical dimensionality, with the channel cap structures extending into the core cavity. This dimensional change increases the contact area between the source contact structure and the vertical semiconductor channel, improving electrical connection reliability while maintaining a compact footprint
2Reliability
If channel cap structures with larger contact area are formed, then electrical contact resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The first channel cap layer is formed preliminarily at the bottom of the core cavity before the second channel cap layer is deposited. This preliminary action establishes a foundation for subsequent manufacturing steps, ensuring proper alignment and contact area formation. The sequential formation process allows each layer to be optimized independently, reducing the cumulative precision requirements while achieving the desired large contact area
Solution Approach 2:
The channel cap structures are nested within the core cavity, with the first channel cap layer positioned at the cavity bottom and the second channel cap layer formed over it. This nesting approach allows the contact structures to be integrated within the existing memory device architecture without requiring external space, thereby achieving expanded contact area while maintaining compact dimensions and manageable manufacturing precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable channel cap structures that improve electrical contact and memory operations by selectively growing semiconductor materials within the semiconductor structure, enhancing the contact area and reducing resistance, thus improving the performance of three-dimensional memory devices.
Implementation Method 1
selectively growing a Group IV-containing material portion from physically exposed surfaces of the vertical semiconductor channel
Data Source
AI summary
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and a memory opening fill structure located in the memory opening. A Group IV-containing material portion is formed by selective deposition on an end portion of the vertical semiconductor channel. Alternatively, a backside semiconductor cap structure can be formed directly on a bottom surface of the vertical semiconductor channel by selective or non-selective deposition of a semiconductor material.