Memory Subsystem Channel Mapping for Multiple Capacity Modes
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Solution Overview
Problem
Developing memory access protocols for memory sub-systems with varying storage capacities and architectures is time-consuming and resource-intensive, leading to increased latency and decreased efficiency in computing systems.
Innovation Solution
Implementing a memory sub-system controller that enables multiple data capacity modes by associating logical channels with physical channels, allowing the system to operate in either full or reduced capacity modes, and updating memory addresses accordingly to facilitate consistent memory access protocols across different configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If distinct memory access protocols are developed for each memory sub-system configuration, then memory access reliability is improved, but development time and resources increase
Solution Approach 1:
The patent implements a universal memory access protocol that can operate across multiple memory sub-system configurations. The controller includes a stripe parameter determination module that automatically determines stripe parameters based on the actual memory configuration, allowing the same protocol to adapt to different numbers of memory devices, channels, and ranks without requiring separate protocol developments for each configuration.
Solution Approach 2:
The patent changes operational parameters (stripe parameters) dynamically based on the memory sub-system configuration. The controller determines stripe parameters such as stripe width and stripe height according to the detected configuration, enabling the system to maintain reliable operation across different configurations by adjusting parameters rather than developing separate protocols.
2Reliability
If distinct memory access protocols are developed for each memory sub-system configuration, then memory access reliability is improved, but computational resources increase
Solution Approach 1:
The controller implements a single universal memory access protocol handling module that can manage multiple memory sub-system configurations. This universal handler determines stripe parameters based on configuration detection and processes memory access requests accordingly, eliminating the need for multiple specialized protocol implementations and reducing computational overhead.
Solution Approach 2:
The memory controller performs self-configuration by automatically detecting the memory sub-system configuration and determining appropriate stripe parameters without external intervention. This self-service capability reduces the computational resources needed for protocol selection and configuration management.
3Adaptability or versatility
If multiple data capacity modes are enabled, then system adaptability is improved, but device complexity increases
Solution Approach 1:
The patent enables multiple data capacity modes by changing stripe parameters rather than implementing fundamentally different access protocols. The controller determines stripe parameters based on the desired capacity mode (full capacity or reduced capacity), allowing flexible adaptation while maintaining a single underlying protocol structure, thus limiting complexity increase.
4Measurement precision
If configuration-specific protocols are used, then memory access precision is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs a universal memory controller design that can handle multiple memory configurations through parameter determination rather than requiring different hardware implementations for each configuration. This approach maintains precise memory access control while simplifying manufacturing by standardizing the controller architecture.
Data Source
AI summary
A determination is made of whether a memory sub-system operates in a full capacity mode or a reduced capacity mode. The full capacity mode corresponds to accessing data residing at a set of memory devices via a number of physical data channels that corresponds to a number of logical data channels. The reduced capacity mode corresponds to accessing the data via a number of physical data channels that is less than the number of logical data channels. A data structure is updated to include one or more mappings between physical data channels and logical data channels according to the determination. A memory access operation to access a data item at memory cells of at least one of the set of memory devices is executed based on the one or more mappings of the data structure.