3D Memory Channel Connection Layout for Stable Source String Formation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing the degree of integration and stability of manufacturing processes, particularly in the arrangement and connection of vertical channels and source channels, which affects the efficiency and reliability of memory cell strings.
Innovation Solution
The semiconductor memory device incorporates a structure with vertical channels connected through connection patterns, source channels extending in a specific direction, and source select lines surrounding the source channels, along with a manufacturing method that includes forming a source select gate layer, preliminary connection structures, and bonding structures to enhance the integration and stability of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the amount of stacking of memory cells is increased to improve the degree of integration, then the number of memory cells per unit area increases, but the manufacturing complexity and difficulty of arranging vertical channels and source channels increases
Solution Approach 1:
The device is segmented into distinct functional regions: bit line region, interlayer insulating layers and conductive patterns stack, vertical channels, connection patterns, source channels, and source select lines. This segmentation allows each component to be independently optimized and manufactured, reducing overall manufacturing complexity while maintaining high integration
Solution Approach 2:
The patent transitions from two-dimensional planar arrangement to three-dimensional vertical stacking. Memory cells are arranged vertically with interlayer insulating layers and conductive patterns stacked in the first direction, allowing increased storage density without proportionally increasing manufacturing complexity
2Reliability
If vertical channels and source channels are arranged to improve electrical connection, then the efficiency of memory cell strings increases, but the manufacturing precision requirements increase
Solution Approach 1:
Connection patterns are introduced as intermediary structures between vertical channels and source channels. These connection patterns facilitate electrical connection while providing manufacturing tolerance, as they can be formed through standard photolithography and etching processes without requiring ultra-precise alignment
Solution Approach 2:
The bit line, interlayer insulating layers, and conductive patterns are formed first before the vertical channels are created. This preliminary structuring establishes a stable framework that guides subsequent vertical channel formation, reducing the precision requirements for later manufacturing steps
Data Source
AI summary
A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes: a bit line overlapping with a peripheral circuit layer; interlayer insulating layers and conductive patterns alternately stacked in a first direction on the bit line; vertical channels connected to the bit line, the vertical channels penetrating the interlayer insulating layers and the conductive patterns, the vertical channels protruding farther in the first direction than the stacked interlayer insulating layers and the conductive patterns; a connection pattern in contact with a portion of each of the vertical channels that protrudes farther in the first direction than the stacked interlayer insulating layers and the conductive patterns, the connection pattern connecting the vertical channels; a source channel in contact with the connection pattern, the source channel extending in the first direction; and a source select line surrounding the source channel.