3D Non-Volatile Memory Channel Coupling via Dummy Patterns
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Solution Overview
Problem
The integration and operational reliability of two-dimensional non-volatile memory devices are limited, prompting the development of three-dimensional non-volatile memory devices with stacked memory cells, which require improved manufacturing methods and structures to enhance performance and stability.
Innovation Solution
A semiconductor device with a stack structure including channel layers, dummy channel patterns, coupling patterns, bit lines, and well pick-up lines, where the channel patterns and dummy channel patterns are alternately arranged, and impurity-doped pads are used to facilitate improved electrical coupling and manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two-dimensional non-volatile memory device structure is used, then manufacturing process is simple, but integration and operational reliability are limited
Solution Approach 1:
The patent transitions from a two-dimensional memory structure to a three-dimensional structure by stacking multiple memory cell layers vertically. The stack includes alternating insulating layers and gate electrodes with channel layers passing through them, creating vertical memory strings that significantly increase storage density and integration while maintaining manufacturing feasibility through sequential layer formation processes
2Productivity
If three-dimensional stacked structure is implemented, then integration is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct sequential steps: forming insulating layers, forming gate electrodes, forming channel layers, and creating coupling patterns. Each layer type is formed independently with specific doping concentrations and patterns, allowing complex 3D structures to be built through manageable, repeatable process modules that improve integration while controlling manufacturing complexity
Solution Approach 2:
The coupling pattern is formed in advance between adjacent memory strings before final device operation. This preliminary coupling structure pre-establishes electrical connections between dummy channel patterns of different memory strings, simplifying subsequent processing steps and enabling higher integration without proportionally increasing manufacturing complexity
3Reliability
If channel patterns and dummy channel patterns are used, then electrical coupling is improved, but device structure becomes more complex
Solution Approach 1:
The coupling pattern acts as an intermediary element that electrically connects dummy channel patterns from adjacent memory strings. This intermediate structure facilitates electrical coupling and signal distribution between memory cells while maintaining a systematic, repeatable pattern that manages device complexity through modular design rather than ad hoc connections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the manufacturing process and structural stability of semiconductor devices, improving the integration and reliability of three-dimensional non-volatile memory devices by enabling efficient electrical coupling and reliable data storage.
Implementation Method 1
impurity-doped pads are used to facilitate improved electrical coupling
Data Source
AI summary
Provided herein may be a semiconductor device. The semiconductor device may include a stack. The semiconductor device may include channel layers including channel patterns passing through the stack, dummy channel patterns passing through the stack, and a coupling pattern which may be disposed below the stack and couples the channel patterns with the dummy channel patterns. The semiconductor device may include a bit line which is disposed on the stack and coupled with the channel patterns. The semiconductor device may include a well pick-up line which is disposed on the stack and coupled with the dummy channel patterns.


