Semiconductor Memory Channel Data Comparison for Test Time Reduction
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Solution Overview
Problem
The increasing number of channels in three-dimensional integrated circuit packaging leads to a significant challenge in reducing test time due to the potential for defects at numerous junctions, which complicates the process of ensuring data integrity and identifying failed memory cells.
Innovation Solution
A semiconductor memory apparatus is designed with comparison blocks, channel selection detection blocks, and combined output blocks that compare channel data and generate test signals based on select signals, enabling efficient identification of failed channels by determining if all data have the same level, thereby reducing test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of channels is increased to increase data transmission capacity, then the amount of data that can be transmitted increases, but the number of junctions increases leading to more defects and longer test time
Solution Approach 1:
The patent divides the test process into multiple test cycles, where each cycle tests a subset of channels rather than all channels simultaneously. This segmentation allows the test system to handle large numbers of channels in manageable groups, reducing the time required for each individual test while maintaining comprehensive coverage of all channels across multiple cycles.
Solution Approach 2:
The patent implements periodic testing by repeatedly cycling through subsets of channels multiple times. Each test cycle operates periodically on different channel combinations, ensuring that all channels are tested thoroughly across several passes. This periodic approach distributes the total test time across multiple shorter cycles rather than requiring one long continuous test.
2Quantity of substance
If the number of channels is increased to increase data transmission capacity, then the amount of data that can be transmitted increases, but the complexity of identifying failed memory cells increases
Solution Approach 1:
The patent segments the channel testing into multiple test cycles with different channel subsets. By dividing the large number of channels into smaller groups that are tested in different cycles, the system can identify failed memory cells more systematically. Each test cycle provides targeted information about specific channel subsets, making defect identification more manageable than testing all channels simultaneously.
Solution Approach 2:
The patent uses feedback from multiple test cycles to identify failed memory cells. By analyzing test results across different cycles and channel subsets, the system can pinpoint failed cells through pattern recognition. The feedback mechanism allows the system to narrow down potential failures by comparing results from different test configurations, reducing the complexity of identifying defects in large channel systems.
Data Source
AI summary
A semiconductor memory apparatus includes a first comparison block configured to compare a plurality of channel data with one another and generate a first comparison signal, or output one of the plurality of channel data as the first comparison signal, in response to a plurality of channel select signals; a second comparison block configured to compare the plurality of channel data and generate a second comparison signal when the plurality of channel select signals have a predetermined combination and a channel detection signal has a predetermined logic level; a channel selection detection block configured to enable the channel detection signal when only one channel select signal among the plurality of channel select signals is enabled; and a combined output block configured to enable a test result signal when at least one comparison signal of the first and second comparison signals is enabled.