3D Memory Channel Doping Layout for Reliable High Integration
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Solution Overview
Problem
There is a limitation in ensuring the operational reliability of three-dimensional semiconductor memory devices due to the increased arrangement density of channel structures penetrating stacked conductive layers, which affects the degree of integration and performance.
Innovation Solution
The semiconductor memory device incorporates a gate stack structure with alternating conductive and interlayer insulating layers, featuring channel structures that penetrate the stack, and impurity regions with varying doping concentrations to enhance operational reliability and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the arrangement density of channel structures is increased to improve the degree of integration, then the device complexity increases, but the operational reliability deteriorates
Solution Approach 1:
The patent applies local quality by creating different impurity regions with distinct doping concentrations at specific locations within the channel structure. The first impurity region has a different doping concentration than the second impurity region, allowing localized optimization of electrical properties. This enables the channel to maintain reliable operation even as overall device density increases, resolving the contradiction between integration and reliability.
Solution Approach 2:
The patent changes the doping concentration parameter within the channel structure by introducing multiple impurity regions with different doping levels. This parameter variation allows optimization of carrier concentration and electrical characteristics in different regions, enabling high-density integration while maintaining operational reliability through controlled electrical properties.
2Reliability
If the doping concentration of impurity regions is optimized to improve operational reliability, then the manufacturing precision requirements increase
Solution Approach 1:
The patent segments the channel structure into multiple impurity regions with different doping concentrations. By dividing the channel into distinct regions (first impurity region and second impurity region), each with optimized doping levels, the patent achieves reliable operation while making the doping process more manageable through localized control rather than requiring uniform high-precision doping throughout the entire channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the operational reliability and integration density of the semiconductor memory device by optimizing the doping concentrations in impurity regions, leading to improved GIDL current generation efficiency and reduced leakage currents.
Implementation Method 1
a doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region
Data Source
AI summary
A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.