Memory Device Channel Initializing and Word Line Floating
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Solution Overview
Problem
Current memory devices face challenges in maintaining read reliability due to threshold voltage distribution shifts caused by hole trapping in channel regions, leading to failed read operations.
Innovation Solution
The memory device employs a block decoder, voltage generator, and block voltage controller to perform channel initializing and word line floating operations, discharging channel regions and floating word lines to a positive bias, thereby reducing hole trapping and minimizing read operation failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read operations are performed on memory blocks, then data access is enabled, but hole trapping in channel regions causes threshold voltage distribution shifts leading to read failures
Solution Approach 1:
The patent applies preliminary action by performing channel initializing operations and word line floating operations before read operations to prevent hole trapping. Specifically, the block voltage controller activates pass switches to apply voltages to channel regions and word lines in advance, creating a protective electrical environment that prevents holes from being trapped during subsequent read operations, thereby maintaining threshold voltage stability and read reliability
Solution Approach 2:
The patent implements preliminary anti-action by applying counter-voltages to channel regions and word lines before read operations to offset potential harmful effects. The block voltage controller applies specific voltage levels (e.g., Vch_init to channel regions, Vwl_float to word lines) that create an electrical condition opposing hole accumulation, thus preventing threshold voltage shifts before they can occur during normal read operations
2Reliability
If channel initializing and word line floating operations are performed, then hole trapping is reduced and read reliability is improved, but device complexity increases due to additional control circuits and operations
Solution Approach 1:
The patent applies universality by designing the block voltage controller to perform multiple functions: it controls both channel initializing operations and word line floating operations, and can selectively activate different pass switches (first pass switch, second pass switch) depending on the operational phase. This multi-functional controller consolidates what could be separate control circuits into a single integrated unit, reducing overall device complexity while maintaining the necessary protective operations
Solution Approach 2:
The patent implements merging by combining the control of channel initializing and word line floating operations into a single block voltage controller unit. Additionally, the global line groups (first global line group, second global line group) are merged with local line groups through shared pass switches, creating an integrated voltage distribution network that simplifies the control architecture while enabling comprehensive protection against hole trapping
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances read reliability by preventing hole trapping and shifting of threshold voltage distributions, thus improving the accuracy and success rate of read operations in memory devices.
Implementation Method 1
a voltage generator configured to generate an operating voltage for an operation performed on the first blocks and the second blocks
Implementation Method 2
perform a channel initializing operation of discharging channel regions of the selected block and a shared block
Implementation Method 3
perform a word line floating operation on the selected block and the shared block after the channel initializing operation, and wherein the word line floating operation floats word lines of the selected block and the shared block to a positive bias
Data Source
AI summary
A memory device having improved read reliability includes: first blocks coupled to a first global line group and second blocks coupled to a second global line group; a voltage generator configured to generate an operating voltage for an operation performed on the first blocks and the second blocks; a block decoder configured to generate a block select signal for selecting a memory block on which a main operation is to be performed from among the first blocks as a selected block; and a block voltage controller configured to control the block decoder and the voltage generator to: perform a channel initializing operation of discharging channel regions of the selected block and a shared block which is selected from among the second blocks according to the block select signal; and perform a word line floating operation on the selected block and the shared block after the channel initializing operation.