3D Memory Channel Layer Crystallization With Fewer Grain Boundaries
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Solution Overview
Problem
In three-dimensional nonvolatile memory devices, achieving a crystalline semiconductor channel layer with reduced electrical resistance and noise is challenging due to the inhibition of single crystallization by crystal nuclei and metal-assisted crystallization processes, which result in a high number of crystal grain boundaries.
Innovation Solution
Incorporating additives like carbon, nitrogen, or fluorine in the channel layer, particularly near the memory layer, to trap crystal nuclei and enhance the trapping effect, allowing for single crystallization through metal-induced lateral crystallization (MILC) or metal-induced crystallization (MIC) annealing treatments, thereby reducing crystal grain boundaries and improving electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If metal-assisted crystallization process is used to form the channel layer, then the crystallization speed is improved, but the number of crystal grain boundaries increases
Solution Approach 1:
The patent removes metal catalysts from the crystallization process entirely, replacing them with a thermal annealing process that achieves single-crystal formation without introducing foreign metal particles that would create grain boundaries. This extraction of the metal-assisted mechanism eliminates the source of excessive grain boundaries while maintaining crystallization capability through controlled thermal treatment.
Solution Approach 2:
The patent changes the crystallization parameters by using high-temperature annealing (typically 400-600°C) in a controlled atmosphere without metal catalysts. This parameter change from metal-assisted to thermal-driven crystallization, combined with specific annealing time and temperature control, achieves single-crystal formation with minimal grain boundaries.
2Reliability
If single crystallization is achieved through conventional methods, then the electrical resistance is reduced, but the process complexity increases
Solution Approach 1:
The patent employs self-service mechanisms where the semiconductor layer itself undergoes spontaneous single-crystal transformation during standard annealing processes used for other purposes (such as stress relief or defect repair). The crystallization occurs as a natural consequence of the annealing treatment rather than requiring a separate, complex crystallization step, thereby reducing overall process complexity.
Solution Approach 2:
The patent merges the crystallization function with existing annealing steps in the manufacturing process. By combining multiple objectives (stress relief, defect repair, and single-crystal formation) into a single annealing treatment, the process complexity is reduced while achieving the desired electrical characteristics through unified process integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a channel layer with fewer crystal grain boundaries, reduced electrical resistance, and enhanced electrical characteristics of the memory cells, improving data storage performance.
Implementation Method 1
Incorporating additives like carbon, nitrogen, or fluorine in the channel layer, particularly near the memory layer, to trap crystal nuclei and enhance the trapping effect
Implementation Method 2
allowing for single crystallization through metal-induced lateral crystallization (MILC) or metal-induced crystallization (MIC) annealing treatments
Implementation Method 3
MILC or metal-induced crystallization (MIC) annealing treatments
Data Source
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AI summary
A semiconductor storage device (1) according to an embodiment includes a stacked body (LM) including a plurality of conductive layers (WL, SGD, SGS) and a plurality of insulating layers (OL) alternately stacked, and a plurality of pillars (PL) each including a core material (CR) extending in the stacked body (LM) in a first direction intersecting a face of each of the plurality of conductive layers (WL, SGD, SGS), a semiconductor layer (CN) covering a side face of the core material (CR), and a multi-layered insulating layer (ME) stacked on a side face of the semiconductor layer (CN), the semiconductor layer (CN) being crystalline, the multi-layered insulating layer (ME) including a charge storage layer (CT), wherein each of the semiconductor layers (CN) includes a crystal structure in which the appearance number of crystal grain boundaries per 1 µm in the first direction is less than 2 near to at least a first end in the first direction, and an additive that includes one or more of carbon, nitrogen, oxygen, and fluorine.