Memory Channel Impedance Control via HDI Segmentation

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Solution Overview

Problem

In memory subsystems, the multi-drop bus topology leads to increased capacitive loads and impedance discontinuities, limiting communication speed due to capacitive loading and undesirable phenomena like multiple reflections and resonance, which existing technologies struggle to address effectively.

Innovation Solution

The implementation of High Density Interconnect (HDI) technology to control impedance in channels between memory controllers and memory devices, using micro-vias and microstrip traces, along with programmable I/O drivers and interface circuits, to enhance signal integrity and match impedance across the communication path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a multi-drop bus topology is used to connect memory controller and multiple DIMMs, then the system can support multiple memory devices, but capacitive loading increases and impedance discontinuities occur, limiting communication speed

Engineering Contradiction:

Improvecommunication speedVSAvoidcapacitive loading

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The channel is segmented into multiple sections with impedance matching structures positioned at specific intervals. Each segment between DIMMs is designed with controlled impedance characteristics, and impedance matching structures are placed at boundaries to isolate the capacitive loading effects of individual DIMMs, preventing them from collectively degrading signal quality across the entire bus.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Impedance matching structures serve as intermediary elements between the memory controller and DIMMs, and between adjacent DIMMs. These structures act as buffer zones that match the impedance transitions, reducing reflections and isolating the harmful capacitive effects of each DIMM from affecting the entire communication channel.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If more DIMMs are added to the multi-drop configuration, then memory capacity increases, but additional capacitive loads and impedance discontinuity points decrease maximum communication speed

Engineering Contradiction:

Improvememory capacityVSAvoidcommunication speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The channel is divided into multiple controlled impedance segments, with each segment designed to maintain signal integrity despite the presence of multiple DIMMs. Impedance matching structures are strategically positioned at segment boundaries to prevent capacitive loading from propagating across the entire bus, allowing more DIMMs to be connected without proportionally degrading communication speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The impedance characteristics of the channel are carefully controlled and adjusted through the use of impedance matching structures. By modifying the impedance parameters at critical points (such as at each DIMM connection point and at the controller interface), the system can accommodate additional DIMMs while maintaining optimal signal transmission conditions and communication speed.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If impedance discontinuity is present in the channel, then multiple reflections and resonance occur, but these phenomena inherently decrease maximum communication speed

Engineering Contradiction:

Improvesignal integrityVSAvoidcommunication speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The impedance matching structures are designed to utilize and control the inevitable impedance discontinuities at DIMM connection points. Rather than attempting to eliminate all discontinuities, the invention converts these potentially harmful reflections into controlled impedance transitions that actually improve overall signal integrity by preventing uncontrolled reflections and resonance, thereby enabling higher communication speeds.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

4Manufacturing precision

If HDI technology is used to control impedance, then manufacturing precision requirements increase, but channel bandwidth and signal integrity improve

Engineering Contradiction:

Improveimpedance control precisionVSAvoidmanufacturing complexity

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The channel is segmented into multiple controlled impedance sections, with impedance matching structures positioned at specific intervals. This segmentation allows each section to be designed and manufactured with focused precision requirements, rather than requiring the entire channel to meet uniform high-precision standards, thereby reducing overall manufacturing complexity while maintaining signal integrity.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8675429B1Optimal channel design for memory devices for providing a high-speed memory interface

Publication Date: 2014.03.18 GOOGLE LLC

AI summary

A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.