3D Nonvolatile Memory Channel Hole Fabrication via Intermediary Layer
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Solution Overview
Problem
The challenge in fabricating 3D nonvolatile memory devices is forming channel holes with a vertical profile, as the etching of interlayer dielectric and sacrificial layers with different etch rates makes it difficult to maintain a constant diameter, especially as the device integration degree increases.
Innovation Solution
A method involving the alternation of interlayer dielectric and sacrificial layers over a substrate, where the sacrificial layers' thickness decreases from bottom to top, and the formation of first and second holes with specific etching processes to create a channel layer and grooves, allowing for the uniform formation of gate electrode layers in contact with the memory layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interlayer dielectric layers and sacrificial layers are alternately stacked and etched to form channel holes, then the integration degree of the device is improved, but the manufacturing precision of channel hole diameter deteriorates due to different etch rates of the layers
Solution Approach 1:
A first insulation layer is introduced as an intermediary material between the interlayer dielectric layers and sacrificial layers. This intermediary layer has an etch rate that is slower than both the interlayer dielectric layer and the sacrificial layer, allowing it to act as a buffer that compensates for the different etch rates of the adjacent layers during channel hole formation, thereby maintaining a more uniform channel hole diameter throughout the stacked structure.
Solution Approach 2:
The etch rate parameter is strategically varied by selecting materials with different etch characteristics. The first insulation layer is specifically chosen to have a slower etch rate compared to the interlayer dielectric and sacrificial layers. This parameter change creates a controlled etching progression where the slower-etching insulation layer compensates for the faster etching of other layers, resulting in improved channel hole diameter uniformity.
2Productivity
If the height of the stacked structure is increased to improve integration degree, then the device capacity is improved, but the difficulty of forming channel holes with vertical profile increases due to accumulated etch rate differences
Solution Approach 1:
The first insulation layer serves as a mediator that distributes and balances the etching effects throughout the increased height of the stacked structure. By positioning this slower-etching layer at regular intervals, the cumulative effect of etch rate differences is mitigated, allowing vertical profiles to be maintained even in taller stacked structures with higher integration degrees.
Solution Approach 2:
The stacked structure is segmented by introducing the first insulation layer at periodic intervals among the interlayer dielectric and sacrificial layers. This segmentation creates multiple smaller etching zones rather than one continuous long etching path, allowing better control over the vertical profile formation in each segment and reducing the cumulative error from etch rate differences.
3Reliability
If a constant diameter channel hole is formed to uniformly secure memory cell characteristics, then the reliability is improved, but the device complexity increases due to the need for additional insulation layers
Solution Approach 1:
The first insulation layer acts as a simple intermediary that passively controls etch rate without requiring complex active control mechanisms. This straightforward material insertion achieves the reliability goal of uniform memory cell characteristics through a relatively simple structural addition, minimizing the increase in device complexity while effectively solving the etch rate differential problem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures the uniformity of memory cell characteristics by controlling the channel hole diameter and gate electrode thickness, enhancing the integration density and reliability of the nonvolatile memory device.
Implementation Method 1
selectively etching the stacked structure to form a channel hole passing through the stacked structure
Data Source
AI summary
A method for fabricating a nonvolatile memory device includes forming a stacked structure having a plurality of interlayer dielectric layers and a plurality of sacrificial layers wherein interlayer dielectric layers and sacrificial layers are alternately stacked over a substrate, forming a first hole exposing a part of the substrate by selectively etching the stacked structure, forming a first insulation layer in the first hole, forming a second hole exposing the part of the substrate by selectively etching the first insulation layer, and forming a channel layer in the second hole.